Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
ADDRESS
5DH
R/W
R
DESCRIPTION
SPDIF input status bits 15 to 0 right channel read-out
SPDIF input status bits 31 to 16 right channel read-out
SPDIF input status bits 39 to 32 right channel read-out
5EH
R
5FH
R
SPDIF output
50H
R/W SPDIF output valid; left to right channel status bit copy; power control and SPDIF output
selection setting
51H
52H
53H
54H
55H
56H
60H
61H
62H
63H
64H
R/W SPDIF output status bits 39 to 24 left channel setting
R/W SPDIF output status bits 23 to 8 left channel setting
R/W SPDIF output status bits 7 to 0 left channel setting
R/W SPDIF output status bits 39 to 24 right channel setting
R/W SPDIF output status bits 23 to 8 right channel setting
R/W SPDIF output status bits 7 to 0 right channel setting
R/W reserved for manufacturers evaluation and should be kept untouched for normal operation
R/W reserved for manufacturers evaluation and should be kept untouched for normal operation
R/W reserved for manufacturers evaluation and should be kept untouched for normal operation
R/W reserved for manufacturers evaluation and should be kept untouched for normal operation
R/W reserved for manufacturers evaluation and should be kept untouched for normal operation
Device ID
7EH
R
device ID; version
Software reset
7FH
R/W restore L3-bus defaults
12.2 Read/write registers mapping
12.2.1 SYSTEM SETTINGS
Table 25 Register address 00H
BIT
15
14
13
12
11
10
9
8
Symbol
EXPU
−
PON_XTAL XTL_DIV4
PLL
XTL_DIV3
XTL_DIV2
XTL_DIV1 XTL_DIV0
Default
0
0
1
0
1
0
0
0
BIT
7
6
5
4
3
2
1
0
Symbol
MODE3
MODE2
MODE1
MODE0
ws_detct_EN ws_detct_set CLKOUT_ CLKOUT_
SEL1
SEL0
Default
0
0
1
0
1
0
1
0
2003 Apr 10
40
NXP [ NXP ]
