Philips Semiconductors
Preliminary specification
Stereo audio codec with SPDIF interface
UDA1355H
12 REGISTER MAPPING
In this chapter the register addressing of the microcontroller interface of the UDA1355H is given. In Section 12.1, the
mapping of the readable and writable registers is given. The explanation of the register definitions are explained in
Sections 12.2 and 12.3.
12.1 Address mapping
Table 24 Register map settings
ADDRESS
R/W
DESCRIPTION
System settings
00H
R/W crystal clock power-on setting; crystal clock and PLL divider settings; MODE and WS detector
settings; clock output setting
01H
02H
03H
04H
R/W I2S-bus output format settings
R/W I2S-bus input format settings
R/W reserved for manufacturers evaluation and should be kept untouched for normal operation
R/W analog power and clock settings
Interpolator
10H
11H
12H
13H
14H
R/W master volume control settings
R/W mixer volume settings
R/W sound feature and bass boost and treble settings
R/W gain select; de-emphasis and mute settings
R/W DAC polarity; noise shaper selection; mixer; source selection; silence detector and interpolator
oversampling settings
18H
19H
1AH
1BH
1CH
1DH
1EH
R
mute and silence detector status read-out
R/W resonant bass boost coefficient k1 setting
R/W resonant bass boost coefficient km setting
R/W resonant bass boost coefficient a1 setting
R/W resonant bass boost coefficient a2 setting
R/W resonant bass boost coefficient b1 setting
R/W resonant bass boost coefficient b2m setting
Decimator
20H
R/W ADC gain settings
21H
R/W ADC mute and PGA gain settings;
R/W ADC polarity and DC cancellation settings
22H
28H
R
mute status and overflow ADC read-out
SPDIF input
30H
40H
59H
5AH
5BH
5CH
R/W SPDIF power control and SPDIF input settings
R/W reserved for manufacturers evaluation and should be kept untouched for normal operation
R
R
R
R
SPDIF LOCK; bit error information and SPDIF encoder output status read-out
SPDIF input status bits 15 to 0 left channel read-out
SPDIF input status bits 31 to 16 left channel read-out
SPDIF input status bits 39 to 32 left channel read-out
2003 Apr 10
39
NXP [ NXP ]
