Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 45 Event Counter set 2 Register (EC2R)
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
11C
EC5 [9:0] 31 to 22
EC4 [9:0] 21 to 12
EC3 [11:0] 11 to 0
R
R
R
Event Counter Five: this is the fourth 10-bit counter
Event Counter Four: this is the third 10-bit counter
Event Counter Three: this is the second 12-bit counter
Table 46 Event Counter set 1 Source Select Register 1 (EC1SSR)
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
E4
−
31 to 24
−
reserved
ECS2 [5:0] 23 to 18 RW Event Counter 2 Source: this 6 bit value addresses one of the status bits
ECEN2
17
16
RW Event Counter 2 Enable: if this bit is set, event counter 2 is enabled
RW Event Counter 2 Clear: writing a logic 1 to this bit will clear event counter 2
ECCLR2
ECS1 [5:0] 15 to 10 RW Event Counter 1 Source: this 6 bit value addresses one of the status bits
ECEN1
9
8
RW Event Counter 1 Enable: if this bit is set event counter 1 is enabled
RW Event Counter 1 Clear: writing a logic 1 to this bit will clear event counter 1
RW Event Counter 0 Source: this 6 bit value addresses one of the status bits
RW Event Counter 0 Enable: if this bit is set event counter 0 is enabled
RW Event Counter 0 Clear: writing a logic 1 to this bit will clear event counter 0
ECCLR1
ECS0 [5:0] 7 to 2
ECEN0
1
0
ECCLR0
Table 47 Event Counter set 2 Source Select Register (EC2SSR)
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
E8
−
31 to 24
−
reserved
ECS5 [5:0] 23 to 18 RW Event Counter 5 Source: this 6 bit value addresses one of the status bits
ECEN5
17
16
RW Event Counter 5 Enable: if this bit is set the event counter 5 is enabled
RW Event Counter 5 Clear: writing a logic 1 to this bit will clear event counter 5
ECCLR5
ECS4 [5:0] 15 to 10 RW Event Counter 4 Source: this 6 bit value addresses one of the status bits
ECEN4
9
8
RW Event Counter 4 Enable: if this bit is set event counter 4 is enabled
RW Event Counter 4 Clear: writing a logic 1 to this bit will clear event counter 4
RW Event Counter 3 Source: this 6 bit value addresses one of the status bits
RW Event Counter 3 Enable: if this bit is set event counter 3 is enabled
RW Event Counter 3 Clear: writing a logic 1 to this bit will clear event counter 3
ECCLR4
ECS3 [5:0] 7 to 2
ECEN3
1
0
ECCLR3
Table 48 Status Bit Addresses (SBA)
ADDRESS
STATUS BIT
(HEX)
EVENTS TO BE COUNTED
00
01
02
03
PPEF
PABO
number of PCI Parity errors
number of PCI Access errors
PPED
RPS_I1
every PCI clock cycle with ‘data’ parity error
number of RPS interrupts Task 1
1998 Apr 09
53
NXP [ NXP ]
