Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 50 Event Counter Threshold set 2 Register (ECT2R)
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
F0
ECT6 [9:0]
31 to 22
RW
Event Counter 5 Threshold: this is the threshold for the
fourth 10-bit counter; see note 1
ECT5 [9:0]
21 to 12
11 to 0
RW
RW
Event Counter 4 Threshold: this is the threshold for the third
10-bit counter; see note 1
ECT4 [11:0]
Event Counter 3 Threshold: this is the threshold for the
second 12-bit counter; see note 1
Note
1. Each of these threshold values shows the limit up to which the related counter will run before it sets it interrupt status
bit.
7.8
Video processing
7.8.1
THE REAL TIME VIDEO INTERFACE
The real time video interface consists of two bidirectional 8-bit wide ports transporting colour difference samples and
luminance samples in a byte sequential manner. Each of the two video ports (A and B) has its own clock pin, pixel
qualifier and horizontal and vertical sync signal pin. The sync signal can be optionally coded in SAV and EAV codes
according to the D1 standard (SMPTE125M or CCIR 656). The two 8-bit ports can be combined to form a single 16-bit
wide YUV port to be compatible to the DMSD2 output format.
D1_A
PXQ_A
HS_A
VS_A
LLC_A
LLC_B
VS_B
HS_B
PXQ_B
D1_B
handbook, full pagewidth
VIDEO DATA STREAM
INITIAL SETTINGS OF
DUAL D1 INTERFACE
INITIAL SETTINGS OF
DUAL D1 INTERFACE
VIDEO DATA STREAM
HANDLING
HANDLING
VID_a
SIO_a
52H
SIO_b
50H
VID_b
54H
56H
MHB049
Fig.8 The real time video interface.
1998 Apr 09
56
NXP [ NXP ]
