Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.8.2
DD1: DUAL D1 (CCIR 656, SMPTE125M), I/O
Cb-Y-Cr-Y 8-bit wide stream
7.8.2.1
In this mode two video ports with YUV 4 : 2 : 2 sampling scheme are available. Each D1 port has an I/O capability and
has a separate clock input and separate sync lines. In this format the pixel rate is equivalent to the clock rate LLC.
The colour difference signal sample and luminance signal sample (straight binary) are byte-wise multiplexed into the
same 8-bit wide data stream, with sequence and timing in accordance with CCIR 656 recommendation (respectively
according to D1 for 60 Hz application). The incoming and scaled data are reformatted to 16-bit for the HPS data path and
the corresponding reference signals are generated. A discontinuous data stream is supported by accepting or generating
a pixel/byte qualifying signal (PXQ = 1: qualified pixel, PXQ = 0: invalid data, see Fig.9). The start condition for
synchronizing to the correct Cb-Y-Cr-Y sequence is given by the selected horizontal reference signal. The sequence
increments only with qualified bytes.
handbook, full pagewidth
LLC_x
PXQ_x
D1_x (7 to 0)
HS_x
Cb
Y
Cr
Y
Cb
Y
MHB050
Fig.9 Timing of PXQ_x for serial 8-bit data input at the D1_x port.
1998 Apr 09
57
NXP [ NXP ]
