Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
ADDRESS
STATUS BIT
(HEX)
EVENTS TO BE COUNTED
number of RPS interrupts Task 0
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
RPS_I0
RPS_LATE1
RPS_LATE0
RPS_E1
RPS_E0
RPS_TO1
RPS_TO0
UPLD
number of RPS late errors for Task 1
number of RPS late errors for Task 0
number of RPS errors for Task 1
number of RPS errors for Task 0
number of time outs for RPS Task 1
number of time outs for RPS Task 0
time for upload, in PCI clocks
DEBI_S
DEBI_E
IIC_S
time DEBI is busy, in PCI clocks
number of DEBI events in total
time I2C-bus is busy, in PCI clocks
number of I2C-bus errors in total
number of protection hits
IIC_E
A2_in
A2_out
A1_in
number of protection hits
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
number of protection hits
A1_out
AFOU
number of protection hits
number of audio FIFOs overflows/underflows in total
number of video FIFO protection violations in total
number of video FIFOs overflows/underflows in total
V_PE
VFOU
FIDA
number of odd/even fields on port A (defined via FIDESA)
number of odd/even fields on port B (defined via FIDESB)
number of active edges as defined in the GPIO registers; see Table 43
number of active edges as defined in the GPIO registers; see Table 43
number of active edges as defined in the GPIO registers; see Table 43
number of active edges as defined in the GPIO registers; see Table 43
number of threshold overflows from EC1, EC2, EC4 and EC5 in total
number of threshold overflows of EC3S
FIDB
PIN3
PIN2
PIN1
PIN0
ECS
EC3S
EC0S
number of threshold overflows of EC0S
PRQ
time from REQ# to GNT#, in PCI clocks
PMA
time in active master mode, in PCI clocks
RPS_RE1
RPS_PE1
RPS_A1
RPS_RE0
RPS_PE0
RPS_A0
DEBI_TO
DEBI_EF
IIC_EA
IIC_EW
number of RPS register access errors for Task 1
number of page errors for RPS Task 1
time of RPS Task 1 busy, in PCI clocks
number of RPS register access errors for Task 0
number of page errors for RPS Task 0
time of RPS Task 0 busy, in PCI clocks
number of DEBI time out events
number of format errors on DEBI port
number of address errors on the I2C-bus
number of I2C-bus write data errors
1998 Apr 09
54
NXP [ NXP ]
