Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.6
General Purpose Inputs/Outputs (GPIO)
7.6.1
GENERAL
The SAA7146A has four general purpose I/O pins. For example, they could be used to signal to other devices a
power-down mode or to map an internal status bit to it, e.g. to detect a sync lost from the VBLK pin of the SAA7110.
Table 42 GPIO registers
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
GPIO3 control register
E0
GPIO3
GPIO2
GPIO1
GPIO0
31 to 24
23 to 16
15 to 8
7 to 0
RW
RW
RW
RW
GPIO2 control register
GPIO1 control register
GPIO0 control register
Table 43 GPIO control register
BIT 7 BIT 6 BIT 5 BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DESCRIPTION
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
1
0
0
1
1
X
X
X
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
input, no interrupt condition
input, rising edge is interrupt condition
input, falling edge is interrupt condition
input, both edges are interrupt condition
output, fixed constant LOW
output, fixed constant HIGH
reserved
SBA[5] SBA[4] SBA[3] SBA[2] SBA[1] SBA[0] output, monitoring the selected status bits of
PSR or SSR; see Table 48
7.7
Event counter
The event counters in the SAA7146A provide the possibility of obtaining a statistical look at the different interrupt sources.
For this purpose six counters are implemented in two registers (EC1R and EC2R). Each register contains one 12-bit
counter and two 10-bit counters. To be flexible in the information collected in the counters it is possible to map each
status bit to any counter. This is done via the Event Counter Source Select Register (ECSSR). The four 10-bit counters
and the two 12-bit counters are able to select one of the 64 possible sources (see Table 47). In addition to the counting,
it is possible to generate interrupts via threshold values for the counters. These thresholds are kept in the two Event
Threshold Registers (ET1R and ET2R). If a counter exceeds its threshold, it is reset to zero and the corresponding status
bit is set.
Table 44 Event Counter set 1 Register (EC1R)
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
118
EC2 [9:0]
EC1 [9:0]
EC0 [1:0]
31 to 22
21 to 12
11 to 0
R
R
R
Event Counter Two: this is the second 10-bit counter
Event Counter One: this is the first 10-bit counter
Event Counter Zero: this is the first 12-bit counter
1998 Apr 09
52
NXP [ NXP ]
