Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
ADDRESS
STATUS BIT
(HEX)
EVENTS TO BE COUNTED
number of I2C-bus read data errors
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
IIC_ER
IIC_EL
IIC_EF
V3P
number of arbitration losses on the I2C-bus
number of I2C-bus frame errors
number of protection violations for video FIFO 3
number of protection violations for video FIFO 2
number of protection violations for video FIFO 1
number of missed Dwords
V2P
V1P
VF3
VF2
number of missed Dwords
VF1
number of missed Dwords
AF2_in
AF2_out
AF1_in
AF1_out
−
number of missed Dwords
number of missed Dwords
number of missed Dwords
number of missed Dwords
reserved
VGT
number of V_syncs in acquisition of HPS
number of output lines
LNQG
EC5S
EC4S
EC2S
EC1S
number of threshold overflows of EC5
number of threshold overflows of EC4
number of threshold overflows of EC2
number of threshold overflows of EC1
Table 49 Event Counter Threshold set 1 Register (ECT1R)
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
EC
ECT2 [9:0]
31 to 22
RW
Event Counter 2 Threshold: this is the threshold for the
second 10-bit counter; see note 1
ECT1 [9:0]
21 to 12
11 to 0
RW
RW
Event Counter 1 Threshold: this is the threshold for the first
10-bit counter; see note 1
ECT0 [11:0]
Event Counter 0 Threshold: this is the threshold for the first
12-bit counter; see note 1
Note
1. Each of these threshold values shows the limit up to which the related counter will run before it sets its interrupt status
bit.
1998 Apr 09
55
NXP [ NXP ]
