Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
114
VF2
12
R
Video FIFO 2 underflow/overflow: this bit is set when the video FIFO 2
has an overflow/underflow. This bit is reset when reloading the DMA
base address or by writing a logic 1 to the VFOU bit in the ISR.
VF1
11
10
9
R
R
R
R
R
Video FIFO 1 overflow: this bit is set when the video FIFO 1 has an
overflow. This bit is reset when reloading the DMA base address or by
writing a logic 1 to the VFOU bit in the ISR.
AF2_in
AF2_out
AF1_in
AF1_out
Audio input FIFO 2 underflow: this bit is set when the audio input
FIFO 2 has an underflow. This bit is reset by restarting the DMA channel
or by writing a logic 1 to the AFOU bit in the ISR.
Audio output FIFO 2 overflow: this bit is set when the audio output
FIFO 2 has an overflow. This bit is reset by restarting the DMA channel
or by writing a logic 1 to the AFOU bit in the ISR.
8
Audio input FIFO 1 underflow: this bit is set when the audio input
FIFO 1 has an underflow. This bit is reset by restarting the DMA channel
or by writing a logic 1 to the AFOU bit in the ISR.
7
Audio output FIFO 1 overflow: this bit is set when the audio output
FIFO 1 has an overflow. This bit is reset by restarting the DMA channel
or by writing a logic 1 to the AFOU bit in the ISR.
−
6
5
4
−
R
R
reserved
VGT
LNQG
Vertical Gate: this bit reflects the vertical gate at the HPS output
Line Qualifier Gate: this bit reflects the horizontal gate at the HPS
output
EC5S
EC4S
EC2S
EC1S
3
2
1
0
R
R
R
R
Event Counter 5 Status: this bit is set when the event counter 5
exceeds its threshold. This bit is reset by writing a logic 1 to the ECS bit
in the ISR.
Event Counter 4 Status: this bit is set when event counter 4 exceeds
its threshold. This bit is reset by writing a logic 1 to the ECS bit in the
ISR.
Event Counter 2 Status: this bit is set when event counter 2 exceeds
its threshold. This bit is reset by writing a logic 1 to the ECS bit in the
ISR.
Event Counter 1 Status: this bit is set when event counter 1 exceeds
its threshold. This bit is reset by writing a logic 1 to the ECS bit in the
ISR.
1998 Apr 09
49
NXP [ NXP ]
