Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
RESET
110
RPS_TO0
21
R
RPS time out error in Task 0: this bit is set when the RPS
Task 0 stays longer than expected in the WAIT state. This bit
is reset by starting a new RPS Task 0.
−
−
−
−
UPLD
DEBI_S
DEBI_E
20
19
18
R
R
R
RPS in UPLOAD: this bit is active while RPS uploads the
working registers from the shadow RAM. The bit in the ISR is
set on the falling edge of this status bit.
DEBI Status: this bit stays set as long as DEBI is processing
or halted by an error. The bit in the ISR is set on the falling
edge of this status bit, which indicates a ‘DEBI Done’.
DEBI Event: this bit is set when one of the two DEBI event
flags (DEBI_EF or DEBI_TO) in the SSR is set. This bit is
reset when a new DEBI command starts. The reset value of
DEBI_TO is a logic 1.
IIC_S
17
R
I2C-bus Status: this bit stays set as long as the I2C-bus is
transmitting data or halted by an error. The bit in the ISR is set
on the falling edge of this status bit, which indicates an ‘I2C
Done’.
−
IIC_E
A2_in
16
15
R
R
I2C-bus Error: this bit gets set when one of the I2C-bus status
bits in the SSR is set. This bit is reset when a new I2C-bus
transfer starts.
−
−
Audio input DMA2 protection: this bit is set when the audio
input DMA2 address generation exceeded an ‘address
boundary’ or hit its ‘limit’ (protection address). It is reset with
starting the DMA channel again.
A2_out
A1_in
14
13
12
R
R
R
Audio output DMA2 protection: this bit is set when the audio
output DMA2 address generation exceeded an ‘address
boundary’ or hit its ‘limit’ (protection address). It is reset with
starting the DMA channel again.
−
−
−
Audio input DMA1 protection: this bit is set when the audio
input DMA1 address generation exceeded an ‘address
boundary’ or hit its ‘limit’ (protection address). It is reset with
starting the DMA channel again.
A1_out
Audio output DMA1 protection: this bit is set when the audio
output DMA1 address generation exceeded an ‘address
boundary’ or hit its ‘limit’ (protection address). It is reset with
starting the DMA channel again.
AFOU
V_PE
11
10
R
R
Audio FIFO Overflow/Underflow: this bit gets set when one
of the four audio FIFOs has an underflow or overflow.
−
−
Video address Protection Error: this bit is set when one of
the video DMAs 1 to 3 has an address protection error during
an active transmission.
VFOU
9
R
Video FIFO Overflow/Underflow: this bit is set if any of the
−
video FIFOs 1, 2 or 3 has an overflow or underflow.
1998 Apr 09
46
NXP [ NXP ]
