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SAA7146AH 参数 Datasheet PDF下载

SAA7146AH图片预览
型号: SAA7146AH
PDF下载: 下载PDF文件 查看货源
内容描述: 多媒体桥接器,高性能倍线器和PCI电路SPCI [Multimedia bridge, high performance Scaler and PCI circuit SPCI]
分类和应用: 商用集成电路PC
文件页数/大小: 144 页 / 646 K
品牌: NXP [ NXP ]
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Philips Semiconductors  
Product specification  
Multimedia bridge, high performance  
Scaler and PCI circuit (SPCI)  
SAA7146A  
OFFSET  
(HEX)  
NAME  
BIT  
TYPE  
DESCRIPTION  
RESET  
110  
FIDA  
8
R
Field ID Port A: via the FIDESA bits in the ‘Initial setting of the  
Dual D1 Interface’ (see Table 66), selected edge(s) of this  
signal will set the corresponding bit in the ISR when enabled.  
FIDB  
PIN3  
PIN2  
PIN1  
PIN0  
ECS  
7
6
5
4
3
2
R
R
R
R
R
R
Field ID Port B: via the FIDESB bits in the ‘Initial setting of the  
Dual D1 Interface’ (see Table 66), selected edge(s) of this  
signal will set the corresponding bit in the ISR when enabled.  
GPIO Pin 3: this bit reflects the state of the general purpose  
pin 3. Via the GPIO register, selected edge(s) of this signal will  
set the corresponding bit in the ISR when enabled.  
GPIO Pin 2: this bit reflects the state of the general purpose  
pin 2. Via the GPIO register, selected edge(s) of this signal will  
set the corresponding bit in the ISR when enabled.  
GPIO Pin 1: this bit reflects the state of the general purpose  
pin 1. Via the GPIO register selected edge(s) of this signal will  
set the corresponding bit in the ISR when enabled.  
GPIO Pin 0: this bit reflects the state of the general purpose  
pin 0. Via the GPIO register selected edge(s) of this signal will  
set the corresponding bit in the ISR when enabled.  
Event Counter Status: this bit reflects the status of the four  
(SSR) event counter status bits EC5S, EC4S, EC2S and  
EC1S.  
EC3S  
EC0S  
1
0
R
R
Event Counter 3 Status: this bit is set when event counter 3  
exceeds its threshold.  
Event Counter 0 Status: this bit is set when event counter 0  
exceeds its threshold.  
Table 39 Secondary status register  
OFFSET  
(HEX)  
NAME  
BIT  
TYPE  
DESCRIPTION  
114  
PRQ  
31  
R
PCI Request Pending: this bit is set while the PCI has asserted its  
REQ# signal and has not received a GNT# yet  
PMA  
30  
29  
R
R
PCI master access: this bit is active as long as the SAA7146A acts as a  
master on the PCI-bus  
RPS_RE1  
RPS Task 1 Register access Error: this bit is set when the LDREG,  
STREG or MASKWRITE command tries to access a non-existing  
register. This bit is reset by writing a logic 1 to the RPS_E1 bit in the ISR  
or when a new RPS Task 1 is started.  
RPS_PE1  
RPS_A1  
28  
27  
R
R
RPS Task 1 Page Error: this bit is set when the RPS Task 1 tries to  
write to an address outside the 4-kbyte page. This bit is reset by writing  
a logic 1 to the RPS_E1 bit in the ISR or when a new RPS Task 1 is  
started.  
RPS Task 1 Active: this bit is set whenever RPS Task 1 is executing  
and not staying in a wait condition or uploading the working registers  
1998 Apr 09  
47  
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