Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.4.4.11 MASKLOAD
The MASKLOAD command is a three Dword command. Its purpose is to modify only portions or selected bits of a
SAA7146A register. The first Dword of the command contains the instruction code and specifies the register to be
modified. The second Dword contains the mask and the third Dword contains the data to be written to the register through
this mask. The mask works as follows: if a bit in the mask is set, the data from the third Dword at the corresponding bit
position will be transferred to the register. If a bit in the mask is zero, the corresponding bit in the register will remain
unchanged.
Table 32 MASKLOAD command first Dword
D31 to D28
D27 to D7
D6 to D0
1100
Reserved
register address
(register offset divided-by-4)
7.4.5
OPERATION
The operation of the RPS is controlled by the enable bits in the main control register 1 (see Table 10). If one of these bits
is set the related RPS task starts its execution with the command addressed by the task related RPS_ADDR register.
When a RPS task is switched on it immediately starts fetching its data via DMA, beginning at the actual address pointers
location. Four Dwords are fetched at a time and loaded into an instruction queue. Operation continues to the end of the
queue at the time the RPS DMA loads the next four Dwords in the RPS list.
To monitor the ongoing execution and the end of RPS there are status and interrupt bits for each task in the Primary
Status Register (PSR) and the Secondary Status Register (SSR), see Tables 38 and 39.
7.4.6
RPS ADDRESS REGISTER
The start address of the RPS list of each task is defined in the RPS address register of the task. The start address must
be Dword aligned.
During an RPS list execution this register works like a program counter. Since the RPS can write data into the main
memory of the system a protection mechanism is implemented. There is a 4-kbyte page in the memory for each task in
which the RPS tasks are allowed to write in. Every write access outside this page will cause an error and the RPS task
will stop immediately. If the corresponding bit in the interrupt enable register is set, an interrupt will be generated. This
protection mechanism can be disabled via the Enable RPS Page Register (ERPSPx) bit. This bit is located at bit 0 of the
RPS page register. A zero enables page errors. This bit is set to 1 after a reset.
Table 33 RPS address register
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
104
RPS_ADDR0
31 to 2
1 and 0
31 to 2
1 and 0
RW
default value: 0
00
108
RPS_ADDR1
RW
default value: 0
00
1998 Apr 09
42
NXP [ NXP ]
