Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.5
Status and interrupts
7.5.1
GENERAL
In order to control the SAA7146A, the status information is collected and stored in two status registers: Primary Status
Register (PSR) and Secondary Status Register (SSR). These two registers follow a hierarchical approach because the
PSR contains summed up information from the SSR. Interrupts can only be generated from the PSR and are enabled
via the Interrupt Enable Register (IER). If an interrupt condition occurs and the interrupt is enabled, the corresponding
bit in the Interrupt Status Register (ISR) is set. These bits can be cleared by writing a logic 1.
Both status registers are read only. Writing a logic 1 into any of the PSR bits causes the corresponding interrupt to be
generated if enabled. Writing a logic 0 has no effect.
Table 38 Primary status register
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
RESET
110
PPEF
31
R
PCI Parity Error: this bit is set when a PCI Parity Error occurs ISR [31]
during any transfer other than ‘real time video data’. The bit in
the ISR is set on the rising edge of this status bit.
PABO
PPED
30
29
R
R
PCI Access Error: this bit is set when the PCI interface starts ISR [30]
an access, and has either a target or master abort. The bit in
the ISR is set on the rising edge of this status bit.
PCI Parity Errors on ‘real time Data’: this bit is set when a
parity error has occurred since the last Vsync or under RPS
since the last wait.
−
RPS_I1
RPS_I0
28
27
26
R
R
R
Interrupt issued by RPS command from Task 1.
Interrupt issued by RPS command from Task 0.
−
−
−
RPS_late1
RPS Task 1 late: this is set by the CHECK_LATE command.
This bit is reset by starting a new RPS Task 1.
RPS_late0
RPS_E1
25
24
R
R
RPS Task 0 late: this is set by the CHECK_LATE command.
This bit is reset by starting a new RPS Task 0.
−
−
RPS_Error Task 1: this bit reflects the status of the RPS
error bits for Task 1 in the secondary status register
(see Table 39). This bit is reset by starting a new RPS Task 1.
RPS_E0
23
22
R
R
RPS_Error Task 0: this bit reflects the status of the RPS
error bits for Task 0 in the secondary status register
(see Table 39). This bit is reset by starting a new RPS Task 0.
−
−
RPS_TO1
RPS time out error in Task 1: this bit is set when the RPS
Task 1 stays longer than expected in the WAIT state. This bit
is reset by starting a new RPS Task 1.
1998 Apr 09
45
NXP [ NXP ]
