Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.4.8
RPS TIME OUT VALUE
These registers contain the values for the time out conditions of the PAUSE and CHECK_LATE commands for each task.
If the selected counter value is zero, the time out generation is disabled.
Table 36 RPS time out value
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
D4
V_TO0
C_TO0
V_ABN0
31
30
29
RW
RW
RW
these two bits determine how the RPS_TO0 is generated;
see Table 37
this bit determines which port the V_sync for the time out check
comes from: a logic 1 selects Port A; a logic 0 selects Port B
−
28
−
reserved
Vsync_Cnt0
27 to 24
RW
this is a 4-bit value which sets the V_sync time out between
1 and 15 V_syncs
PCI_Cnt0
23 to 0
RW
this value specifies after how many PCI clocks a time out
should be detected
D8
V_TO1
C_TO1
V_ABN1
31
30
29
RW
RW
RW
these two bits determine how the RPS_TO1 is generated;
see Table 37
this bit determines which port the V_sync for the time out check
comes from: a logic 1 selects Port A; a logic 0 selects Port B
−
28
−
reserved
Vsync_Cnt1
27 to 24
RW
this is a 4-bit value which sets the V_sync time out between
1 and 15 V_syncs
PCI_Cnt1
23 to 0
RW
this value specifies after how many PCI clocks a time out
should be detected
Table 37 RPS_TOX generation
V_TOX
C_TOX
RPS_TOX GENERATED FORMAT
no time out check
0
0
1
1
0
1
0
1
PCI clock time out check
V_sync time out check
both time out checks
1998 Apr 09
44
NXP [ NXP ]
