Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 34 RPS page register
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
C4
RPS_PAGE0 31 to 12
RW
−
default value: 0
reserved
−
11 to 1
0
ERPSP0
RW
RW
−
Enable RPS Page Register 0
default value: 0
C8
RPS_PAGE1 31 to 12
−
11 to 1
0
reserved
ERPSP1
RW
Enable RPS Page Register 1
7.4.7
LINE COUNTER THRESHOLDS
For the events related to the line counters of the source and the target, (either HPS or BRS) there are two thresholds for
each task in the HBI threshold register (see Table 35). The purpose of this register is to set the HS or HT event flag when
the corresponding line counter has reached the threshold. These thresholds must be written before waiting on the event.
A value of zero as threshold turns the HS or HT event on, for every line.
Table 35 HBI threshold register
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
CC
−
31 to 29
28
−
reserved
TLCS0
RW
Target Line Counter Select for Task 0: this bit defines if the
TLCT0 refers to the HPS (logic 0) or to the BRS (logic 1)
TLCT0
27 to 16
RW
Target Counter Threshold for Task 0: specifies the threshold
for the target line counter
−
15 to 13
12
−
reserved
SLCS0
RW
Source Line Counter Select for Task 0: the bit defines if the
SLCT0 refers to the HPS (logic 0) or to the BRS (logic 1)
SLCT0
11 to 0
RW
Source Line Counter Threshold for Task 0: specifies the
threshold for the source line counter
D0
−
31 to 29
28
−
reserved
TLCS1
RW
Target Line Counter Select for Task 1: this bit defines if the
TLCT refers to the HPS (logic 0) or to the BRS (logic 1)
TLCT1
27 to 16
RW
Target Line Counter Threshold for Task 1: specifies the
threshold for the target line counter
−
15 to 13
12
−
reserved
SLCS1
RW
Source Line Counter Select for Task 1: this bit defines if the
SLCT1 refers to the HPS (logic 0) or to the BRS (logic 1)
SLCT1
11 to 0
RW
Source Line Counter Threshold for Task 1: specifies the
threshold for the source line counter
1998 Apr 09
43
NXP [ NXP ]
