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SAA7146AH 参数 Datasheet PDF下载

SAA7146AH图片预览
型号: SAA7146AH
PDF下载: 下载PDF文件 查看货源
内容描述: 多媒体桥接器,高性能倍线器和PCI电路SPCI [Multimedia bridge, high performance Scaler and PCI circuit SPCI]
分类和应用: 商用集成电路PC
文件页数/大小: 144 页 / 646 K
品牌: NXP [ NXP ]
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Philips Semiconductors  
Product specification  
Multimedia bridge, high performance  
Scaler and PCI circuit (SPCI)  
SAA7146A  
OFFSET  
(HEX)  
NAME  
RW2  
BIT  
TYPE  
DESCRIPTION  
28  
2
RW Specifies the data stream direction of FIFO 2. A logic 0 enables a write  
operation to the PCI memory. A logic 1 enables a read operation from the  
PCI memory.  
Swap2  
1 and 0  
RW endian swapping of all Dwords passing the FIFO 2:  
00 = no swap  
01 = two byte swap (3210 to 2301)  
10 = four byte swap (3210 to 0123)  
11 = reserved  
2C  
NumLines2 27 to 16 RW Number of lines per field: in read mode NumLines defines the number of  
lines to be read from system memory. A logic 0 specifies one line. In write  
mode this register is not used.  
NumBytes2 11 to 0  
RW Number of bytes per line: in read mode this defines the number of bytes  
per line to be read from system memory. A logic 0 specifies one byte. In  
write mode this register is not used.  
30  
34  
38  
BaseOdd3  
31 to 0  
RW PCI base address for odd fields of the upper (or lower if top-down flip is  
selected) left pixel of the transferred field  
BaseEven3 31 to 0  
RW PCI base address for even fields of the upper (or lower if top-down flip is  
selected) left pixel of the transferred field  
ProtAddr3  
31 to 2  
1 and 0  
31 to 0  
RW protection address  
reserved  
3C  
40  
Pitch3  
Page3  
ME3  
RW distance between the start addresses of two consecutive lines of a field  
31 to 12 RW base address of the page table (see Section 7.2.4)  
11  
RW mapping enable; this bit enables the MMU  
reserved  
10 to 8  
7 to 4  
Limit3  
RW interrupt limit; defines the size of the memory range, that raise an  
interrupt, if its boundaries are passed  
PV3  
3
2
RW protection violation handling  
RW3  
RW Specifies the data stream direction of FIFO 3. A logic 0 enables a write  
operation to the PCI memory. A logic 1 enables a read operation from the  
PCI memory.  
Swap3  
1 and 0  
RW endian swapping of all Dwords passing the FIFO 3:  
00 = no swap  
01 = two byte swap (3210 to 2301)  
10 = four byte swap (3210 to 0123)  
11 = reserved  
44  
NumLines3 27 to 16 RW Number of lines per field: in read mode NumLines defines the number of  
lines to be read from system memory. A logic 0 specifies one line. In write  
mode it defines the number of qualified lines to be processed by the BRS  
per field. This will cut off all the following input-lines at the BRS input.  
NumBytes3 11 to 0  
RW Number of bytes per line: in read mode this defines the number of bytes  
per line to be read from system memory. A logic 0 specifies 1 byte. In write  
mode it defines the number of qualified bytes to be processed by the BRS  
per line. This will cut off all the following bytes at the BRS input.  
1998 Apr 09  
23  
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