Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 4 Protection violation handling modes
LIMIT
0000
PV
DESCRIPTION
0
Lock input of FIFO and empty FIFO (only in write mode). Unlock FIFO and start next transfer
using the base address at the detection of BOF.
0000
XXXX(1)
0
1
Restart immediately at base address.
Lock input of FIFO, empty FIFO (only in write mode) and then reset TR_E bit. The next transfer
starts with BOF using the corresponding base address, if the TR_E bit is set again. This setting
is useful for single-shot, that means transferring only one frame of a video stream. Therefore
the protection address has to be the same as the address of the last pixel of the field.
Note
1. X = don’t care.
positive pitch
positive pitch
positive pitch
handbook, full pagewidth
1st line
BaseAddr
2nd line
3rd line
Last line
ProtAddr
(a) positive line pitch
negative pitch
negative pitch
negative pitch
Last line
2nd line
1st line
MGG260
ProtAddr
BaseAddr
(b) positive line pitch
Fig.5 Handling of base and protection address using positive and negative line pitch.
1998 Apr 09
25
NXP [ NXP ]
