Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
AC
BaseA2_in
31 to 0
RW
Base address for audio input Channel 2; this value specifies a
byte address. The lower two bits are forced to zero.
B0
B4
ProtA2_in
31 to 2
RW
protection address for audio input Channel 2; this address
could be used to specify a upper limit for audio access in memory
space
−
1 and 0
31 to 12
11
−
reserve
PageA2_in
MEA2_in
−
RW
RW
−
base address of the page table, see Section 7.2.4
mapping enable; this bit enables the MMU
reserved
10 to 8
7 to 4
LimitA2_in
RW
interrupt limit; defines the size of the memory range, that raise an
interrupt, if its boundaries are passed
PVA2_in
−
3
RW
−
protection violation handling
2 to 0
31 to 0
reserve
B8
BaseA2_out
RW
Base address for audio output Channel 2; this value specifies a
byte address. The lower two bits are forced to zero.
BC
ProtA2_out
31 to 2
RW
protection address for audio output Channel 2; this address
could be used to specify a upper limit for audio access in memory
space
−
1 and 0
31 to 12
11
−
reserved
C0
PageA2_out
MEA2_out
−
RW
RW
−
base address of the page table, see Section 7.2.4
mapping enable; this bit enables the MMU
reserved
10 to 8
7 to 4
LimitA2_out
RW
interrupt limit; defines the size of the memory range, that raise an
interrupt, if its boundaries are passed
PVA2_out
3
RW
protection violation handling
−
2 to 0
−
reserved
1998 Apr 09
27
NXP [ NXP ]
