Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
The video channels provide 32 bits of data signals and
4 bits of Byte Enable (BE) signals, End-Of-Line (EOL),
End-Of-Window (EOW), Begin-Of-Field (BOF),
Line-Locked Clock (LLC), Odd/Even signal (OE) and a
Valid Data (VD) signal. To start a video data transfer, e.g.
via video DMA Channel 3, this channel must first be
included in the internal arbitration scheme. This is
achieved by setting the corresponding TR_E bit
(see Table 10). If a TR_E bit is not set, the corresponding
FIFO is reset.
shown in Fig.5. If using negative pitch the first line starts at
base address + pitch.
In ‘none-RPS’ mode the SAA7146A supports the
displaying of interlaced video data by using the two
different base addresses (BaseOdd and BaseEven) and
vertical start phases (YPE6 to YPE0 and YPO6 to YPO0)
for odd and even fields.
Using the protection address, system memory could be
kept of from prohibited write accesses. If the PCI pointer of
the current transfer reaches or exceeds the protection
address, the SAA7146A stops this transfer and an
interrupt is initiated. No interrupt is set if a protection
violation occurs due to the programming that was done
before the channel has been switched on. To prevent one
field from being transferred into memory, set its base
address (BaseOdd or BaseEven) to the same value as the
protection address.
In read mode, which is offered by Channels 2 and 3, the
FICO requests a PCI transfer with the next BOF. Data is
provided by the PCI master module. The FICO calculates
the PCI address autonomously, starting with the base
address of the corresponding field. Only the received data
will be filled into the FIFO. FIFO 3 offers the possibility to
read video information from PCI memory, e.g. from the
frame buffer. This could be achieved by using the
NumBytes and the NumLines register, which defines the
size of the source picture, so that the DMA control is able
to synchronize itself to the source frame. FIFO 2 does the
same if reading clip information from memory.
If the Protection Violation (PV) handling bit and the limit
register are reset, the following data will be ignored until
detection of the End-Of-Window (EOW) signal. In read
mode the DMA control also waits for this signal, to start the
next data transfer. If the PV bit is set, the input of the FIFO
will be locked and the FIFO will be emptied. If the FIFO is
empty the TR_E bit is reset. This feature could be used for
a single capture mode, if the protection address is the
same address as the last pixel in this field. With that, the
SAA7146A will write one field into system memory and
then stop.
To support the Binary Ratio Scaler (BRS) included in the
SAA7146A, which only provides the possibility of
horizontal upscaling, the DMA control 3 can be applied to
perform line repetition by reading lines up to four times
from PCI memory. This feature is controlled by the vertical
scaling ratio in outbound mode (see Table 66). This ratio
specifies the number of times each line should be read:
00 = only once, 01 = twice, and so on.
If the limit register of any DMA channel (video, VBI data or
audio) has a value other than ‘0000’ the continuous write
mode is chosen. If the actual PCI address hits the
protection address and the PV bit is zero, the FINC stops
the current transfer, sets an interrupt and resets the actual
address to the base address. Regarding this, the
protection address could be used to define a memory
space to which data is sent. The SAA7146A offers the
possibility to monitor the filling level of this memory space.
The limit register defines an address limit, which generates
an interrupt if passed by the actual PCI address pointer.
‘0001’ means an interrupt will be generated if the lower
6 bits (64 bytes) of the PCI address are zero. ‘0010’
defines a limit of 128 bytes, ‘0011’ one of 256 bytes, and
so on up to 1 Mbyte defined by ‘1111’. This interrupt range
can be calculated as follows:
In the event of FIFO underflow, i.e. if the BRS or the
clipping unit respectively tries to read data from the FIFO,
even if the DMA control was not able to fill any data until
that moment, the reading unit tries to synchronize itself to
the outgoing data stream as soon as possible. In this way
the reading of invalid data is minimized. If the clipping unit
receives no data, it will disable the associated pixels.
The behaviour of the BRS depends on the selected read
mode which is described in Section 7.10.
In the event of FIFO overflow, i.e. if the scaler tries to
transfer data although the FIFO is full, the FIFO input
control locks the FIFO for the incoming data. During FIFO
overflow the PCI address of the incoming data will be
increased, over writing itself each time, if the scaler
transfers data, which has been clipped, the same
mechanism is used to improve PCI performance.
Range = 2(5 + Limit) bytes.
The protection handling modes such as those selected by
the PV bit and the contents of the limit register are shown
in Table 4.
The SAA7146A is able to handle a negative pitch.
With that, top-down-flip of the transmitted fields or frames
is possible. A negative pitch (MSB = 1) leads to a different
definition of the protection and the base address, as
1998 Apr 09
24
NXP [ NXP ]
