Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
The protection violation handling differs only if the limit
register and the PV bit are programmed to zero. The audio
DMA channel does not wait for the EOF signal, like the
video ones. It does not generate interrupts. The interrupt
range specified by the limit register is defined in the same
way as described in Section 7.2.2. The audio DMA
channels try immediately to transfer data after setting the
transfer enable bits. All registers for audio DMA control,
which are the base address, the protection address and
the control bits are listed in the following Table 5, except
the input control bits (Burst, Threshold), which are listed in
Table 6.
7.2.3
AUDIO DMA CONTROL
The SAA7146A provides up to four audio DMA channels,
each using a FIFO of 24 Dwords. Two channels are read
only (A1_in and A2_in) and two channels are write only
(A1_out and A2_out). Because audio represents a
continuous data stream, which is neither line nor field
dependent, the audio DMA control offers only one base
address (BaseAxx) and no pitch register. For FIFO
overflow and underflow the handling of these channels is
done in the same way as the video DMA channels
(see Section 7.2.2).
Table 5 Audio DMA control register
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
94
BaseA1_in
31 to 0
RW
base address for audio input Channel 1; this value specifies a
byte address
98
ProtA1_in
31 to 2
RW
protection address for audio input Channel 1; this address
could be used to specify a upper limit for audio access in memory
space
−
1 to 0
31 to 12
11
−
reserved
9C
PageA1_in
MEA1_in
−
RW
RW
−
base address of the page table, see Section 7.2.4.
mapping enable; this bit enables the MMU
reserved
10 to 8
7 to 4
LimitA1_in
RW
interrupt limit; defines the size of the memory range, that
generates interrupt, if its boundaries are passed
PVA1_in
−
3
RW
−
protection violation handling
2 to 0
31 to 0
reserved
A0
A4
BaseA1_out
RW
Base address for audio output Channel 1; this value specifies a
byte address. The lower two bits are forced to zero.
ProtA1_out
31 to 2
RW
protection address for audio output Channel 1; this address
could be used to specify a upper limit for audio access in memory
space
−
1 and 0
31 to 12
11
−
reserved
A8
PageA1_out
MEA1_out
−
RW
RW
−
base address of the page table, see Section 7.2.4.
mapping enable; this bit enables the MMU
reserved
10 to 8
7 to 4
LimitA1_out
RW
interrupt limit; defines the size of the memory range, that
generates an interrupt, if its boundaries are passed
PVA1_out
3
RW
protection violation handling
−
2 to 0
−
reserved
1998 Apr 09
26
NXP [ NXP ]
