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g
logic
address
FIFO1
FIFO2
MEMORY MANAGEMENT
physical address
UNIT
(MMU)
FIFO
INPUT
CONTROL
(FINC)
FIFO3
video/audio
data streams
AUDIO FIFO1 OUT
AUDIO FIFO1 IN
AUDIO FIFO2 OUT
AUDIO FIFO2 IN
data
FIFO
CONTROL
(FICO)
byte enable
bus command
CE
PCI
EOT
MODULE
MASTER
new Tr
channel select
PCI-bus
INTERNAL ARBITRATION
CONTROL
PCI
MODULE
SLAVE
(INTAC)
bus requests
data
address
DEBI data/request
REGISTER
AND
SHADOW RAM
REGISTER PROGRAMMING
REGISTER
SETS
SEQUENCER
(RPS)
2
I C-BUS REGISTER
ERROR MANAGER
(EMA)
interrupts
MHB047
Fig.4 Block diagram of the PCI interface.
NXP [ NXP ]
