Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 3 Video DMA control registers
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
00
BaseOdd1
31 to 0
RW PCI base address for odd fields of the upper (or lower if pitch is
negative) left pixel of the transferred field
04
08
BaseEven1 31 to 0
RW PCI base address for even fields of the upper (or lower if pitch is
negative) left pixel of the transferred field
ProtAddr1
−
31 to 2
1 and 0
31 to 0
RW protection address
−
reserved
0C
10
Pitch1
RW distance between the start addresses of two consecutive lines of a single
field
Page1
ME1
−
31 to 12 RW base address of the page table (see Section 7.2.4)
11
RW mapping enable; this bit enables the MMU
reserved
10 to 8
7 to 4
−
Limit1
RW interrupt limit; defines the size of the memory range, that raise an
interrupt, if its boundaries are passed
PV1
−
3
2
RW protection violation handling
−
reserved
Swap1
1 and 0
RW endian swapping of all Dwords passing the FIFO 1:
00 = no swap
01 = two bytes swap (3210 to 2301)
10 = four bytes swap (3210 to 0123)
11 = reserved
14
NumLines1 27 to 16 RW Number of lines per field; it defines the number of qualified lines to be
processed by the HPS per field. This will cut off all the following input lines
at the HPS input.
NumBytes1 11 to 0
RW Number of pixels per line; it defines the number of qualified pixels to be
processed by the HPS per line. This will cut off all the following pixels at
the HPS input.
18
1C
20
BaseOdd2
31 to 0
RW PCI base address for odd fields of the upper (or lower if top-down flip is
selected) left pixel of the transferred field
BaseEven2 31 to 0
RW PCI base address for even fields of the upper (or lower if top-down flip is
selected) left pixel of the transferred field
ProtAddr2
−
31 to 2
1 and 0
31 to 0
RW protection address
−
reserved
24
28
Pitch2
Page2
ME2
RW distance between the start addresses of two consecutive lines of a field
31 to 12 RW base address of the page table (see Section 7.2.4)
11
RW mapping enable; this bit enables the MMU
reserved
−
10 to 8
7 to 4
−
Limit2
RW interrupt limit; defines the size of the memory range, that raise an
interrupt, if its boundaries are passed
PV2
3
RW protection violation handling
1998 Apr 09
22
NXP [ NXP ]
