Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 1 Configuration space registers
ADDRESS
NAME
BIT
TYPE
DESCRIPTION
(HEX)
00
Device ID
31 to 16
RO 7146H
SAA7146A
Vendor ID
15 to 0
RO 1131H
Philips
04
Status Register
31
−
−
detected parity error
29
received master abort
received target abort
DEVSEL# timing medium
data parity error detected
fast back-to-back capable
fast back-to-back enable
parity error response
bus master enable
28
−
26 and 25
RO 01
−
24
23
RO 1
RW
RW
RW
RW
Command
Register
9
6
2
1
memory space
08
Class Code
Revision ID
Latency
31 to 8
7 to 0
15 to 8
RO 048000H other multimedia device
RO 01H
RW
reading these 8 bits returns 01H
0C
10
this register specifies, in units of PCI-bus clocks, the
value of the latency timer for this PCI-bus master
Base Address
Register
31 to 9
8 to 0
RW
RO
this value must be added to the register offset to claim
access to the programming registers; the lower 8 bits
are forced to zero
2C
3C
Subsystem ID
31 to 16
15 to 0
RO
RO
this value will be loaded after a PCI reset from external
hardware using the I2C-bus; the default value is 0000H
Subsystem
vendor ID
this value will be loaded after a PCI reset from external
hardware using the I2C-bus; the default value is 0000H
Max_Lat
31 to 24
23 to 16
15 to 8
RO
this value will be loaded after a PCI reset from external
hardware using the I2C-bus; the default value is 26H
Min_Gnt
RO
this value will be loaded after a PCI reset from external
hardware using the I2C-bus; the default value is 0FH
Interrupt Pin
RO 01H
The interrupt pin register tells which interrupt pin the
device uses. This device uses interrupt pin INTA#.
When these bits are read they return 01H.
Interrupt Line
7 to 0
RW
the interrupt line register tells which input of the system
interrupt controller the device’s interrupt pin is
connected to
1998 Apr 09
20
NXP [ NXP ]
