Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.15.4.4 Command word description
To configure and initiate a transfer there are 3 PCI memory mapped command words. A DEBI register upload after
writing to DEBI_COMMAND starts the transfer process.
Table 95 DEBI_CONFIG
OFFSET
NAME
XIRQ_EN
XRESUME
−
BIT
31
TYPE
RW
RW
−
DESCRIPTION
enable external interrupt on GPIO3
resume block transfer when XIRQ was de-asserted
reserved
7CH
30
29
FAST
28
RW
−
enable fast mode (short trwi time)
reserved
−
27 and 26
25 to 22
21 and 20
TIMEOUT [3:0]
SWAP
RW
RW
timer set-up value (PCI clock cycles)
endian swap type:
00: straight - don’t swap
01: 2-byte swap
10: 4-byte swap
11: reserved
SLAVE16
INCREMENT
INTEL
19
18
RW
RW
RW
RW
−
indicates that slave is able to serve 16-bit cycles
enables address increment for block transfer
Intel style bus handshake if HIGH, else Motorola style
timer enable (active LOW)
reserved
17
TIEN
16
−
15 to 0
Table 96 DEBI_COMMAND
OFFSET
NAME
BIT
TYPE
DESCRIPTION
80H
BLOCKLENGTH 31 to 17
[14:0]
RW
BLOCKLENGTH > 4: block transfer length in bytes
4 ≥ BLOCKLENGTH > 0: immediate transfer 1 to 4 bytes
BLOCKLENGTH = 0: reserved
WRITE_N
A16_IN
16
RW
RW
transfer direction (write if LOW)
slave target start address
15 to 0
Table 97 DEBI_PAGE
OFFSET
NAME
BIT
TYPE
DESCRIPTION
84H
DEBI_PAGE
PAGE_EN
−
31 to 12
11
RW
RW
−
DEBI page table address (not used if PAGE_EN = 0)
enable address paging
reserved
10 to 0
Table 98 DEBI_AD
OFFSET
NAME
DEBI_AD
BIT
TYPE
DESCRIPTION
88H
31 to 0
RW
data input/output in immediate mode or DMA start address
for block transfer (Dword aligned, DEBI_AD [1:0] have to be
set to logic 0)
1998 Apr 09
110
NXP [ NXP ]
