Philips Semiconductors
Product specification
9-bit video input processor
SAA7113H
15.2.20 SUBADDRESS 13H
Table 51 Output control SA 13, D7, D4, D3, D1 and D0
FUNCTION
BIT
LOGIC LEVEL
DATA BIT
Analog test select (AOSL)
AOUT connected to internal test point 1
AOSL1
AOSL0
AOSL1
AOSL0
AOSL1
AOSL0
AOSL1
AOSL0
0
0
0
1
1
0
1
1
D1
D0
D1
D0
D1
D0
D1
D0
AOUT connected to input AD1
AOUT connected to input AD2
AOUT connected to internal test point 2
Field ID polarity if selected on RTS1 or RTS0 outputs if RTSE1, RTSE0 (subaddress 12H) are set to 1111
Default
FIDP
FIDP
0
1
D3
D3
Inverted
Selection bit for status byte functionality OLDSB
Default status information; see Table 55
OLDSB
OLDSB
0
1
D4
D4
Old status information, for compatibility
reasons; see Table 55
Analog-to-digital converter output bits on VPO7 to VPO0 in bypass mode (VIPB = 1, used for test purposes)
ADLSB; note 1
AD8 to AD1 (MSBs) on VPO7 to VPO0
AD7 to AD0 (LSBs) on VPO7 to VPO0
ADLSB
ADLSB
0
1
D7
D7
Note
1. Analog-to-digital converter selection via MODE3 to MODE0 (subaddress 02H; see Figs 35 to 38).
1999 Jul 01
65
NXP [ NXP ]
