Philips Semiconductors
Product specification
9-bit video input processor
SAA7113H
15.2.18 SUBADDRESS 11H
Table 48 Output control 1 SA 11
FUNCTION
BIT
LOGIC LEVEL DATA BIT
Colour on (COLO)
Automatic colour killer
Colour forced on
COLO
COLO
0
1
D0
D0
YUV decoder bypassed (VIPB)
Processed data to VPO output
VIPB
VIPB
0
1
D1
D1
ADC data to VPO output; dependent on mode settings
Output enable real-time (OERT)
RTS0, RTS1, RTCO high-impedance inputs
OERT
OERT
0
1
D2
D2
RTS0, RTCO active, RTS1 active, if RTSE13 to RTSE10 = 0000
Output enable YUV data (OEYC)
VPO-bus high-impedance
OEYC
OEYC
0
1
D3
D3
Output VPO-bus active or controlled by RTS1; see Table 19
Selection of horizontal lock indicator for RTS0, RTS1 outputs
Standard horizontal lock indicator (low-passed)
HLSEL
HLSEL
0
1
D4
D4
Fast lock indicator (use is recommended only for high performance input
signals)
General purpose switch [available on pin RTS0, if control byte RTSE03 to RTSE00 (subaddress 12H) is set to
0010]
LOW
HIGH
GPSW0
GPSW0
0
1
D5
D5
CM99 compatibility to SAA7199 (CM99)
Default value
CM99
CM99
0
1
D6
D6
To be set only if SAA7199 (digital encoder) is used for re-encoding in
conjunction with RTCO
General purpose switch [available on pin RTS1, if control byte RTS103 to RTS100 (subaddress 12H) is set to
0010]
LOW
HIGH
GPSW1
GPSW1
0
1
D7
D7
1999 Jul 01
62
NXP [ NXP ]
