Philips Semiconductors
Product specification
9-bit video input processor
SAA7113H
15.2.19 SUBADDRESS 12H
Table 49 RTS0 output control SA 12
D3 TO D0
RTSE03 RTSE02 RTSE01 RTSE00
RTS0 OUTPUT CONTROL
Reserved
0
0
0
0
0
0
0
1
VIPB (subaddress 11H bit 1) = 0: reserved
VIPB (subaddress 11H bit 1) = 1: LSBs of the 9-bit ADCs
GPSW0 level (subaddress 11H, bit 5)
0
0
0
0
1
1
0
1
HL (horizontal lock indicator); selectable via HLSEL (subaddress 11H, bit 4)
HSEL = 0: standard horizontal lock indicator
HSEL = 1: fast horizontal lock indicator (use is not recommended for
sources with unstable timebase e.g. VCRs)
VL (vertical and horizontal lock)
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
DL (vertical and horizontal lock and colour detected)
PLIN (PAL/SECAM sequence; LOW: PAL/DR line is present)
HREF_HS, horizontal reference signal: indicates valid data on the
VPO-bus. The positive slope marks the beginning of a new active line.
The pulse width is dependent on the data type selected by the control
registers LCR2 to LCR24 (subaddress 41H to 57H; see Tables 4 and 61)
data type 0 to 6 8 to 15: HIGH period 1440 LLC-cycles (720 samples;
see Fig.28)
data type 7 (upsampled raw data): HIGH period programmable in LLC8
steps via HSB7 to HSB0, HSS7 to HSS0 (subaddress 06H and 07H), fine
position adjustment via HDEL1 to HDEL0 (subaddress 10H, bits 5 and 4)
HS, programmable width in LLC8 steps via HSB7 to HSB0 and
HSS7 to HSS0 (subaddress 06H and 07H), fine position adjustment in
LLC2 steps via HDEL1 to HDEL0 (subaddress 10H, bits 5 and 4)
1
0
0
0
HQ (HREF gated with VREF)
1
1
0
0
0
1
1
0
ODD, field identifier; HIGH = odd field; see vertical timing diagrams
Figs 29 and 30
VS (vertical sync; see vertical timing diagrams Figs 29 and 30)
V123 (vertical pulse; see vertical timing diagrams Figs 29 and 30)
1
1
1
0
1
1
1
0
0
1
0
1
VGATE (programmable via VSTA8 to VSTA0 and VSTO8 to VSTO0,
subaddresses 15H, 16H and 17H)
VREF (programmable in two positions via VRLN, subaddress 10H, bit 3)
1
1
1
1
1
1
0
1
FID (position and polarity programmable via VSTA8 to VSTA0,
subaddresses 15H and 17H and FIDP, subaddress 13H bit 3)
1999 Jul 01
63
NXP [ NXP ]
