Philips Semiconductors
Product specification
9-bit video input processor
SAA7113H
15.2 I2C-bus detail
15.2.2 SUBADDRESS 01H
The I2C-bus receiver slave address is 48H/49H.
Subaddresses 14H, 18H to 1EH, 20H to 3FH and
63H to FFH are reserved.
Table 26 Horizontal increment delay
FUNCTION
No update
IDEL3 IDEL2 IDEL1 IDEL0
1
1
1
1
1
0
1
1
0
1
0
0
15.2.1 SUBADDRESS 00H (READ ONLY REGISTER)
Minimum delay
Recommended
position
Table 25 Chip version SA 00
LOGIC LEVELS
FUNCTION
Maximum delay
0
0
0
0
ID07
ID06
ID05
ID04
Chip Version (CV)
CV3
CV2
CV1
CV0
The programming of the horizontal increment delay is
used to match internal processing delays to the delay of
the ADC. Use recommended position only.
15.2.3 SUBADDRESS 02H
Table 27 Analog control 1 SA 02
CONTROL BITS D3 TO D0
FUNCTION(1)
MODE 3 MODE 2 MODE 1 MODE 0
Mode 0: CVBS (automatic gain) from AI11 (pin 4)
Mode 1: CVBS (automatic gain) from AI12 (pin 7)
Mode 2: CVBS (automatic gain) from AI21 (pin 43)
Mode 3: CVBS (automatic gain) from AI22 (pin 1)
Mode 4: reserved
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Mode 5: reserved
Mode 6: Y (automatic gain) from AI11 (pin 4) + C (gain adjustable via
GAI28 to GAI20) from AI21 (pin 43); note 2
Mode 7: Y (automatic gain) from AI12 (pin 7) + C (gain adjustable via
GAI28 to GAI20) from AI22 (pin 1); note 2
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
1
Mode 8: Y (automatic gain) from AI11 (pin 4) + C (gain adapted to Y gain)
from AI21 (pin 43); note 2
Mode 9: Y (automatic gain) from AI12 (pin 7) + C (gain adapted to Y gain)
from AI22 (pin 1); note 2
Modes 10 to 15: reserved
Notes
1. Mode select (see Figs 35 to 42).
2. To take full advantage of the YC-modes 6 to 9 the I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1
(full luminance bandwidth).
1999 Jul 01
51
NXP [ NXP ]
