ISP1362
Single-chip USB OTG controller
Philips Semiconductors
Table 71: HcµPInterruptEnable register: bit description
Bit
Symbol
Description
15 to 10
9
-
reserved
OTG_IRQ_
0 — power-up value
InterruptEnable
1 — enables the OTG_IRQ interrupt
0 — power-up value
8
7
6
5
4
3
2
1
0
ATL_IRQ_
InterruptEnable
1 — enables the ATL_IRQ interrupt
0 — power-up value
INTL_IRQ_
InterruptEnable
1 — enables the INT_IRQ interrupt
0 — power-up value
ClkReady
1 — enables the ClkReady interrupt
HCSuspendedEnable 0 — power-up value
1 — enables the HC suspended interrupt
0 — power-up value
OPRInterruptEnable
1 — enables the 32-bit operational register’s interrupt
0 — power-up value
EOTInterruptEnable
1 — enables the EOT interrupt
0 — power-up value
ISTL_1Interrupt
Enable
1 — enables the ISTL_1 interrupt
0 — power-up value
ISTL_0Interrupt
Enable
1 — enables the ISTL_0 interrupt
0 — power-up value
SOFInterrupt
Enable
1 — enables the SOF interrupt
15.5 HC miscellaneous registers
15.5.1 HcChipID register (R: 27H)
This register contains the ID of the ISP1362. The upper byte identifies the product
name (here 36H stands for the ISP1362). The lower byte indicates the revision
number of the product including engineering samples. Table 72 contains the bit
description of the register.
Code (Hex): 27 — read only
Table 72: HcChipID register: bit description
Bit
Symbol
Access Value
3630H
Description
15 to 0 CHIPID[15:0] R
Chip ID of the ISP1362.
15.5.2 HcScratch register (R/W: 28H/A8H)
This register is for the HCD to save and restore values when required. The bit
description is given in Table 73.
Code (Hex): 28 — read
Code (Hex): A8 — write
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
98 of 150
NXP [ NXP ]
