ISP1362
Single-chip USB OTG controller
Philips Semiconductors
Table 76: HcBufferStatus register: bit description…continued
Bit
7
Symbol
Description
-
reserved
6
ISTL1_ActiveStatus 0 — The ISTL1 buffer is not accessed by the slave host.
1 — The ISTL1 buffer is accessed by the slave host.
5
4
ISTL0_ActiveStatus 0 — The ISTL0 buffer is not accessed by the slave host.
1 — The ISTL0 buffer is accessed by the slave host.
Reset_HW
PingPong
Reg
0 to 1 — resets internal hardware ping pong register to 0
when ATL_Active is 0. The hardware ping pong register
can be read from bit 10 of this register.
1 to 0 — has no effect.
3
2
1
0
ATL_Active
0 — The HC does not process the ATL buffer.
1 — The HC processes the ATL buffer.
0 — The HC does not process the INTL buffer.
1 — The HC processes the INTL buffer.
0 — The HC does not process the ISTL1 buffer.
1 — The HC processes the ISTL1 buffer.
0 — The HC does not process the ISTL0 buffer.
1 — The HC processes the ISTL0 buffer.
INTL_Active
ISTL1BufferFull
ISTL0BufferFull
15.6.2 HcDirectAddressLength register (R/W: 32H/B2H)
The HcDirectAddressLength register is used for direct addressing of the ISTL, INTL
or ATL buffers. This register specifies the starting address of the buffer and byte count
of the data to be addressed. Therefore, it allows the programmer to randomly access
the buffer. The bit allocation of the register is given in Table 77.
Code (Hex): 32 — read
Code (Hex): B2 — write
Table 77: HcDirectAddressLength register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
Reset
Access
Bit
DataByteCount[15:8]
0
0
0
0
0
0
0
0
R/W
23
R/W
22
R/W
21
R/W
20
R/W
19
R/W
18
R/W
17
R/W
16
Symbol
Reset
Access
Bit
DataByteCount[7:0]
0
0
0
0
0
0
0
R/W
9
0
R/W
8
R/W
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
15
Symbol
Reset
Access
reserved
BufferStartAddress[14:8]
0
0
-
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
100 of 150
NXP [ NXP ]
