ISP1362
Single-chip USB OTG controller
Philips Semiconductors
Code (Hex): 40 — read
Code (Hex): C0 — write
Table 81: HcISTL0BufferPort register: bit description
Bit
Symbol
Access Value
Description
15 to 0 DataWord R/W
[15:0]
0000H
The data in the ISTL0 buffer to be accessed
through this data port.
The HCD is first required to initialize the HcTransferCounter register with the byte
count to be transferred and check the HcBufferStatus register. The HCD then sends
the command (40H for reading from the ISTL0 buffer, and C0H for writing to the
ISTL0 buffer) to the HC through the I/O port of the microprocessor. After the
command is sent, the HCD starts reading data from the ISTL0 buffer or writing data to
the ISTL0 buffer. While the HCD is accessing the buffer, the buffer pointer of ISTL0
also increases automatically. When the pointer has reached the initialized byte count
of the HcTransferCounter register, the HC sets the AllEOTInterrupt bit of the
HcµPInterrupt register to logic 1 and updates the HcBufferStatus register.
15.7.3 HcISTL1BufferPort register (R/W: 42H/C2H)
In addition to the HcDirectAddressData register, the ISP1362 provides this register to
act as another data port for accessing the ISTL1 buffer. The starting address for
accessing the buffer is always fixed at 0000H. Therefore, random access of the ISTL1
buffer is not allowed. The bit description of the register is given in Table 82.
Code (Hex): 42 — read
Code (Hex): C2 — write
Table 82: HcISTL1BufferPort register: bit description
Bit
Symbol
Access Value
Description
15 to 0 DataWord R/W
[15:0]
0000H
The data in the ISTL1 buffer to be accessed
through this data port.
The HCD is first required to initialize the HcTransferCounter register with the byte
count to be transferred and check the HcBufferStatus register. The HCD then sends
the command (42H for reading from the ISTL1 buffer, and C2H for writing to the
ISTL1 buffer) to the HC through the I/O port of the microprocessor. After the
command is sent, the HCD starts reading data from the ISTL1 buffer or writing data to
the ISTL1 buffer. While the HCD is accessing the buffer, the buffer pointer of ISTL1
also increases automatically. When the pointer has reached the initialized byte count
of the HcTransferCounter register, the HC sets the AllEOTInterrupt bit in the
HcµPInterrupt register to logic 1 and updates the HcBufferStatus register.
15.7.4 HcISTLToggleRate register (R/W: 47H/C7H)
The rate of toggling between ISTL0 and ISTL1 is programmable. The
HcISTLToggleRate register is provided for programming the required toggle rate in
the range of 0 ms to 15 ms at intervals of 1 ms. The bit allocation of the register is
shown in Table 83.
Code (Hex): 47 — read
Code (Hex): C7 — write
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
102 of 150
NXP [ NXP ]
