ISP1362
Single-chip USB OTG controller
Philips Semiconductors
15.4.2 HcDMAConfiguration register (R/W: 21H/A1H)
Table 65 contains the bit allocation of the HcDMAConfiguration register.
Code (Hex): 21 — read
Code (Hex): A1 — write
Table 65: HcDMAConfiguration register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
Reset
Access
Bit
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
-
7
6
5
3
2
1
0
Symbol
DMACounter
Enable
BurstLen[1:0]
DMA
Enable
Buffer_Type_Select[2:0]
DMARead
WriteSelect
Reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 66: HcDMAConfiguration register: bit description
Bit
Symbol
Description
reserved
15 to 8
7
-
DMACounterEnable
0 — reserved
1 — DMA counter is enabled. Once the counter is
enabled, the HCD must initialize the HcTransferCounter
register to a non-zero value for DREQ to be raised after
the DMAEnable bit is set to HIGH.
6 to 5
BurstLen[1:0]
00 — single-cycle burst DMA
01 — 4-cycle burst DMA
10 — 8-cycle burst DMA
11 — reserved
I/O bus with 32-bit data path width supports only single
and four cycle DMA burst.
4
DMAEnable
0 — DMA is disabled
1 — DMA is enabled
This bit needs to be reset when the DMA transfer is
completed.
3 to 1
Buffer_Type_Select
[2:0]
Bit 3 Bit 2 Bit 1 Buffer Type
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
ISTL0 (default)
ISTL1
INTL
ATL
Direct Addressing
0
DMAReadWriteSelect 0 — read from the buffer memory of the HC
1 — write to the buffer memory of the HC
9397 750 12337
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 06 January 2004
94 of 150
NXP [ NXP ]
