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ISP1160BD 参数 Datasheet PDF下载

ISP1160BD图片预览
型号: ISP1160BD
PDF下载: 下载PDF文件 查看货源
内容描述: 嵌入式通用串行总线主控制器 [Embedded Universal Serial Bus Host Controller]
分类和应用: 总线控制器微控制器和处理器外围集成电路数据传输时钟
文件页数/大小: 88 页 / 1864 K
品牌: NXP [ NXP ]
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ISP1160  
Embedded USB Host Controller  
Philips Semiconductors  
7. Functional description  
7.1 PLL clock multiplier  
A 6 MHz to 48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip.  
This allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No  
external components are required for the operation of the PLL.  
7.2 Bit clock recovery  
The bit clock recovery circuit recovers the clock from the incoming USB data stream  
by using a 4 times oversampling principle. It is able to track jitter and frequency drift  
as specified in Universal Serial Bus Specification Rev. 2.0.  
7.3 Analog transceivers  
Two sets of transceivers are embedded in the chip for downstream ports with USB  
connector type A. The integrated transceivers are compliant with the Universal Serial  
Bus Specification Rev. 2.0. These transceivers interface directly with the USB  
connectors and cables through external termination resistors.  
7.4 Philips Serial Interface Engine (SIE)  
The Philips SIE implements the full USB protocol layer. It is completely hardwired for  
speed and needs no firmware intervention. The functions of this block include:  
synchronization pattern recognition, parallel to serial conversion, bit (de)stuffing,  
CRC checking and generation, Packet IDentifier (PID) verification and generation,  
address recognition, and handshake evaluation and generation.  
8. Microprocessor bus interface  
8.1 Programmed I/O (PIO) addressing mode  
A generic PIO interface is defined for speed and ease-of-use. It also allows direct  
interfacing to most microcontrollers. To a microcontroller, the ISP1160 appears as a  
memory device with a 16-bit data bus and uses the A0 address line to access internal  
control registers and FIFO buffer RAM. Therefore, the ISP1160 occupies only two  
I/O ports or two memory locations of a microprocessor. External microprocessors can  
read from or write to the ISP1160’s internal control registers and FIFO buffer RAM  
through the Programmed I/O (PIO) operating mode. Figure 3 shows the  
Programmed I/O interface between a microprocessor and the ISP1160.  
9397 750 11371  
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.  
Product data  
Rev. 04 — 04 July 2003  
8 of 88  
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