ISP1160
Embedded USB Host Controller
Philips Semiconductors
Table 2:
Pin description for LQFP64…continued
Symbol[1]
Pin
Type
Description
DACK_N
27
I
HC DMA acknowledge input; when not in use, this pin must
be connected to VCC via an external 10 kΩ resistor
TEST_HIGH
INT
28
29
-
this pin must be connected to VCC via an external 10 kΩ
resistor
O
HC interrupt output; programmable level, edge triggered
and polarity; see Section 10.4.1
n.c.
30
31
32
-
no connection; leave this pin open
no connection; leave this pin open
n.c.
O
I
RESET_N
reset input (Schmitt trigger); a LOW level produces an
asynchronous reset (internal pull-up resistor)
NDP_SEL
33
I
indicates to the HC software the Number of Downstream
Ports (NDP) present:
0 — select 1 downstream port
1 — select 2 downstream ports
only changes the value of the NDP field in the
HcRhDescriptorA register; both ports will always be
enabled; see Section 10.3.1
(internal pull-up resistor)
EOT
34
I
DMA master device to inform the ISP1160 of end of DMA
transfer; active level is programmable; when not in use, this
pin must be connected to VCC via an external 10 kΩ
resistor; see Section 10.4.1
DGND
35
36
37
-
-
-
digital ground
n.c.
no connection; leave this pin open
TEST_LOW
this pin must be connected to DGND via an external 10 kΩ
resistor
n.c.
38
39
40
-
-
I
no connection; leave this pin open
TEST_LOW
H_WAKEUP
this pin must be connected to DGND via a 1 MΩ resistor
HC wake-up input; generates a remote wake-up from the
suspend state (active HIGH); when not in use, this pin must
be connected to DGND via an external 10 kΩ resistor
(internal pull-down resistor)
n.c.
41
-
no connection; leave this pin open
H_SUSPEND 42
O
I
HC suspend state indicator output; active HIGH
XTAL1
43
crystal input; connected directly to a 6 MHz crystal; when
this pin is connected to an external clock source,
pin XTAL2 must be left open
XTAL2
44
O
crystal output; connected directly to a 6 MHz crystal; when
pin XTAL1 is connected to an external clock source, this
pin must be left open
DGND
45
46
-
digital ground
H_PSW1_N
O
power switching control output for downstream port 1;
open-drain output
H_PSW2_N
47
O
power switching control output for downstream port 2;
open-drain output
9397 750 11371
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 04 July 2003
6 of 88
NXP [ NXP ]
