ISP1160
Embedded USB Host Controller
Philips Semiconductors
Table 17: HcInterruptEnable register: bit description
Bit
Symbol
Description
31
MIE
MasterInterruptEnable by the HCD: A logic 0 is ignored by the
HC. A logic 1 enables interrupt generation by events specified in
other bits of this register.
30 to 7
6
-
reserved
RHSC
0 — ignore
1 — enable interrupt generation due to Root Hub Status Change
5
4
3
2
FNO
UE
0 — ignore
1 — enable interrupt generation due to frame Number Overflow
0 — ignore
1 — enable interrupt generation due to Unrecoverable Error
RD
SF
0 — ignore
1 — enable interrupt generation due to Resume Detect
0 — ignore
1 — enable interrupt generation due to Start of frame
1
0
-
reserved
SO
0 — ignore
1 — enable interrupt generation due to Scheduling Overrun
10.1.6 HcInterruptDisable register (R/W: 05H/85H)
Each disable bit in the HcInterruptDisable register corresponds to an associated
interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is
coupled with the HcInterruptEnable register. Thus, writing a logic 1 to a bit in this
register clears the corresponding bit in the HcInterruptEnable register, whereas
writing a logic 0 to a bit in this register leaves the corresponding bit in the
HcInterruptEnable register unchanged. On a read, the current value of the
HcInterruptEnable register is returned.
Code (Hex): 05 — read
Code (Hex): 85 — write
Table 18: HcInterruptDisable register: bit allocation
Bit
31
MIE
0
30
29
28
27
reserved
0
26
25
24
Symbol
Reset
Access
Bit
0
0
0
0
0
0
R/W
23
R/W
22
R/W
21
R/W
20
R/W
19
R/W
18
R/W
17
R/W
16
Symbol
Reset
Access
Bit
reserved
0
0
0
0
0
0
0
R/W
9
0
R/W
8
R/W
15
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
Symbol
Reset
Access
reserved
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
9397 750 11371
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 04 July 2003
43 of 88
NXP [ NXP ]
