ISP1160
Embedded USB Host Controller
Philips Semiconductors
Code (Hex): 82 — write
Table 12: HcCommandStatus register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
Reset
Access
Bit
reserved
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
23
22
21
20
19
18
17
16
Symbol
Reset
Access
Bit
reserved
SOC[1:0]
0
R
0
R
0
R
0
R
0
R
0
R
0
R
9
0
R
8
15
14
13
12
11
10
Symbol
Reset
Access
Bit
reserved
0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
Symbol
Reset
Access
reserved
0
HCR
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 13: HcCommandStatus register: bit description
Bit
Symbol
-
Description
31 to 18
17 to 16
reserved
SOC[1:0]
SchedulingOverrunCount: The field is incremented on each
scheduling overrun error. It is initialized to 00B and wraps around
at 11B. It will be incremented when a scheduling overrun is
detected even if SchedulingOverrun in HcInterruptStatus has
already been set. This is used by HCD to monitor any persistent
scheduling problems.
15 to 1
0
-
reserved
HCR
HostControllerReset: This bit is set by the HCD to initiate a
software reset of the HC. Regardless of the functional state of the
HC, it moves to the USBSuspend state in which most of the
operational registers are reset, except those stated otherwise, and
no Host bus accesses are allowed. This bit is cleared by the HC
upon the completion of the reset operation. The reset operation
must be completed within 10 µs. This bit, when set, does not
cause a reset to the Root Hub and no subsequent reset signaling
should be asserted to its downstream ports.
10.1.4 HcInterruptStatus register (R/W: 03H/83H)
This register provides the status of the events that cause hardware interrupts. When
an event occurs, the HC sets the corresponding bit in this register. When a bit is set, a
hardware interrupt is generated if the interrupt is enabled in the HcInterruptEnable
register (see Section 10.1.5) and bit MasterInterruptEnable is set. The HCD can clear
individual bits in this register by writing logic 1 to the bit positions to be cleared, but
cannot set any of these bits. Conversely, the HC can set bits in this register, but
cannot clear these bits.
9397 750 11371
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 04 July 2003
40 of 88
NXP [ NXP ]
