ISP1160
Embedded USB Host Controller
Philips Semiconductors
Bit
23
22
21
20
19
18
17
16
Symbol
Reset
Access
Bit
FSMPS[7:0]
0
0
0
0
0
0
0
R/W
9
0
R/W
8
R/W
15
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
Symbol
Reset
Access
Bit
reserved
FI[13:8]
0
R/W
7
0
R/W
6
1
R/W
5
0
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
0
R/W
0
Symbol
Reset
Access
FI[7:0]
1
1
0
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 21: HcFmInterval register: bit description
Bit
Symbol
Description
31
FIT
FrameIntervalToggle: The HCD toggles this bit whenever it loads
a new value to FrameInterval.
30 to 16
FSMPS
[14:0]
FSLargestDataPacket: Specifies a value which is loaded into the
Largest Data Packet Counter at the beginning of each frame. The
counter value represents the largest amount of data in bits which
can be sent or received by the HC in a single transaction at any
given time without causing a scheduling overrun. The field value is
calculated by the HCD.
15 to 14
13 to 0
-
reserved
FI[13:0]
FrameInterval: Specifies the interval between two consecutive
SOFs in bit times. The default value is 11999. The HCD must save
the current value of this field before resetting the HC. Setting the
HostControllerReset field of the HcCommandStatus register will
cause the HC to reset this field to its default value. HCD may
choose to restore the saved value upon completing the reset
sequence.
10.2.2 HcFmRemaining register (R: 0EH)
The HcFmRemaining register is a 14-bit down counter showing the bit time remaining
in the current frame.
Code (Hex): 0E — read
Table 22: HcFmRemaining register: bit allocation
Bit
31
FRT
0
30
29
28
27
26
25
24
Symbol
Reset
Access
Bit
reserved
0
R
0
R
0
R
0
R
0
R
0
R
0
R
R
23
22
21
20
19
18
17
16
Symbol
Reset
Access
reserved
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
9397 750 11371
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 04 July 2003
45 of 88
NXP [ NXP ]
