ISP1160
Embedded USB Host Controller
Philips Semiconductors
10.1.5 HcInterruptEnable register (R/W: 04H/84H)
Each enable bit in the HcInterruptEnable register corresponds to an associated
interrupt bit in the HcInterruptStatus register. The HcInterruptEnable register is used
to control which events generate a hardware interrupt. A hardware interrupt is
requested on the host bus when three conditions occur:
• A bit is set in the HcInterruptStatus register
• The corresponding bit in the HcInterruptEnable register is set
• Bit MasterInterruptEnable is set.
Writing a logic 1 to a bit in this register sets the corresponding bit, whereas writing a
logic 0 to a bit in this register leaves the corresponding bit unchanged. On a read, the
current value of this register is returned.
Code (Hex): 04 — read
Code (Hex): 84 — write
Table 16: HcInterruptEnable register: bit allocation
Bit
31
MIE
0
30
29
28
27
reserved
0
26
25
24
Symbol
Reset
Access
Bit
0
0
0
0
0
0
R/W
23
R/W
22
R/W
21
R/W
20
R/W
19
R/W
18
R/W
17
R/W
16
Symbol
Reset
Access
Bit
reserved
0
0
0
0
0
0
0
R/W
9
0
R/W
8
R/W
15
R/W
14
R/W
13
R/W
12
R/W
11
R/W
10
Symbol
Reset
Access
Bit
reserved
0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
Symbol
Reset
Access
reserved
0
RHSC
0
FNO
0
UE
0
RD
0
SF
0
reserved
0
SO
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
9397 750 11371
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 04 July 2003
42 of 88
NXP [ NXP ]
