ISP1160
Embedded USB Host Controller
Philips Semiconductors
Table 11: HcControl register: bit description
Bit
Symbol
-
Description
31 to 11
10
reserved
RWE
RemoteWakeupEnable: This bit is used by the HCD to enable or
disable the remote wake-up feature upon the detection of
upstream resume signaling. When this bit is set and the
ResumeDetected bit in HcInterruptStatus is set, a remote wake-up
is signaled to the host system. Setting this bit has no impact on the
generation of hardware interrupt.
9
RWC
RemoteWakeupConnected: This bit indicates whether the HC
supports remote wake-up signaling. If remote wake-up is
supported and used by the system, it is the responsibility of
system firmware to set this bit during POST. The HC clears the bit
upon a hardware reset but does not alter it upon a software reset.
Remote wake-up signaling of the host system is host-bus-specific
and is not described in this specification.
8
-
reserved
7 to 6
HCFS
HostControllerFunctionalState for USB:
00B — USBReset
01B — USBResume
10B — USBOperational
11B — USBSuspend
A transition to USBOperational from another state causes
start-of-frame (SOF) generation to begin 1 ms later. The HCD may
determine whether the HC has begun sending SOFs by reading
the StartofFrame field of HcInterruptStatus.
This field can be changed by the HC only when in the
USBSuspend state. The HC can move from the USBSuspend
state to the USBResume state after detecting the resume signaling
from a downstream port.
The HC enters USBReset after a software reset and a hardware
reset. The latter also resets the Root Hub and asserts subsequent
reset signaling to downstream ports.
5 to 0
-
reserved
10.1.3 HcCommandStatus register (R/W: 02H/82H)
The HcCommandStatus register is used by the HC to receive commands issued by
the HCD, and it also reflects the HC’s current status. To the HCD, it appears to be a
‘write to set’ register. The HC must ensure that bits written as logic 1 become set in
the register while bits written as logic 0 remain unchanged in the register. The HCD
may issue multiple distinct commands to the HC without concern for corrupting
previously issued commands. The HCD has normal read access to all bits.
The SchedulingOverrunCount field indicates the number of frames with which the HC
has detected the scheduling overrun error. This occurs when the Periodic list does
not complete before EOF. When a scheduling overrun error is detected, the HC
increments the counter and sets the SchedulingOverrun field in the HcInterruptStatus
register.
Code (Hex): 02 — read
9397 750 11371
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 04 — 04 July 2003
39 of 88
NXP [ NXP ]
