74HC373-Q100; 74HCT373-Q100
NXP Semiconductors
Octal D-type transparent latch; 3-state
Table 8.
Dynamic characteristics 74HC373-Q100 …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
th hold time
Conditions
Min
Typ
Max
Unit
Dn to LE; see Figure 11
VCC = 2.0 V
5
5
5
-
-
-
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
[1] tpd is the same as tPLH and tPHL
[2] ten is the same as tPZH and tPZL
[3] tdis is the same as tPLZ and tPHZ
[4] tt is the same as tTHL and tTLH
.
.
.
.
[5] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
Table 9.
Dynamic characteristics 74HCT373-Q100
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 C
[1]
tpd
propagation delay
Dn to Qn; see Figure 8
VCC = 4.5 V
-
-
17
14
30
-
ns
ns
VCC = 5 V; CL = 15 pF
LE to Qn; see Figure 9
VCC = 4.5 V
-
-
16
13
32
-
ns
ns
VCC = 5 V; CL = 15 pF
OE to Qn; see Figure 10
VCC = 4.5 V
[2]
[3]
[4]
ten
tdis
tt
enable time
-
19
18
5
32
30
12
-
ns
ns
ns
ns
ns
disable time
OE to Qn; see Figure 10
VCC = 4.5 V
-
transition time
pulse width
Qn; see Figure 8 and Figure 9
VCC = 4.5 V
-
tW
tsu
th
LE HIGH; see Figure 9
VCC = 4.5 V
16
12
4
set-up time
Dn to LE; see Figure 11
VCC = 4.5 V
6
-
hold time
Dn to LE; see Figure 11
VCC = 4.5 V
4
-
1
-
-
ns
[5]
CPD
power dissipation capacitance
per latch;
41
pF
VI = GND to (VCC 1.5 V)
74HC_HCT373_Q100
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Product data sheet
Rev. 1 — 10 August 2012
13 of 24
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