74HC373-Q100; 74HCT373-Q100
NXP Semiconductors
Octal D-type transparent latch; 3-state
Table 9.
Dynamic characteristics 74HCT373-Q100 …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
th
hold time Dn to LE
Dn to LE; see Figure 11
VCC = 4.5 V
4
-
-
ns
[1] tpd is the same as tPLH and tPHL
.
[2] ten is the same as tPZH and tPZL
[3] tdis is the same as tPLZ and tPHZ
[4] tt is the same as tTHL and tTLH
.
.
.
[5] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
11. Waveforms
Dn input
V
M
t
t
PHL
PLH
90 %
V
M
Qn output
10 %
TLH
t
t
THL
001aae082
Measurement points are given in Table 10.
Fig 8. Propagation delay input (Dn) to output (Qn) and transition time output (Qn)
LE input
V
M
t
W
t
t
PHL
PLH
90 %
Qn output
V
M
10 %
t
t
TLH
THL
001aae083
Measurement points are given in Table 10.
Fig 9. Pulse width latch enable input (LE), propagation delay (LE) to output (Qn) and transition time output (Qn)
74HC_HCT373_Q100
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Product data sheet
Rev. 1 — 10 August 2012
15 of 24
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