74HC373-Q100; 74HCT373-Q100
NXP Semiconductors
Octal D-type transparent latch; 3-state
Table 8.
Dynamic characteristics 74HC373-Q100 …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 40 C to +125 C
[1]
tpd
propagation delay
Dn to Qn; see Figure 8
VCC = 2.0 V
-
-
-
-
-
-
225
45
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
38
LE to Qn; see Figure 9
VCC = 2.0 V
-
-
-
-
-
-
265
53
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
45
[2]
[3]
[4]
ten
tdis
tt
enable time
disable time
transition time
pulse width
set-up time
OE to Qn; see Figure 10
VCC = 2.0 V
-
-
-
-
-
-
225
45
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
38
OE to Qn; see Figure 10
VCC = 2.0 V
-
-
-
-
-
-
225
45
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
38
Qn; see Figure 8 and Figure 9
VCC = 2.0 V
-
-
-
-
-
-
90
18
15
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
tW
LE HIGH; see Figure 9
VCC = 2.0 V
120
24
-
-
-
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
20
tsu
Dn to LE; see Figure 11
VCC = 2.0 V
75
15
13
-
-
-
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
74HC_HCT373_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 10 August 2012
12 of 24
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