74HC373-Q100; 74HCT373-Q100
NXP Semiconductors
Octal D-type transparent latch; 3-state
V
I
OE input
output
V
M
GND
t
t
PZL
PLZ
V
CC
V
LOW-to-OFF
OFF-to-LOW
M
10%
V
OL
t
t
PZH
PHZ
V
OH
90%
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aae307
Measurement points are given in Table 10.
Fig 10. 3-state enable and disable time
V
h
LE input
M
t
t
su
su
t
t
h
V
Dn input
M
001aae084
Measurement points are given in Table 10.
Fig 11. Set-up and hold time data input (Dn) to latch enable input (LE)
Table 10. Measurement points
Type
Input
VM
Output
VM
74HC373-Q100
74HCT373-Q100
0.5VCC
1.3 V
0.5VCC
1.3 V
74HC_HCT373_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 10 August 2012
16 of 24
NXP [ NXP ]
