74HC373-Q100; 74HCT373-Q100
NXP Semiconductors
Octal D-type transparent latch; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
CC
V
CC
V
V
O
I
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 11.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
RL = Load resistor
S1 = Test selection switch
Fig 12. Test circuit for measuring switching times
Table 11. Test data
Type
Input
VI
Load
S1 position
tPHL, tPLH
open
tr, tf
6 ns
6 ns
CL
RL
tPZH, tPHZ
GND
tPZL, tPLZ
VCC
74HC373-Q100
VCC
15 pF, 50 pF
15 pF, 50 pF
1 k
1 k
74HCT373-Q100 3 V
open
GND
VCC
74HC_HCT373_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 10 August 2012
17 of 24