74HC373-Q100; 74HCT373-Q100
NXP Semiconductors
Octal D-type transparent latch; 3-state
10. Dynamic characteristics
Table 8.
Dynamic characteristics 74HC373-Q100
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = 25 C
[1]
tpd
propagation delay
Dn to Qn; see Figure 8
VCC = 2.0 V
-
-
-
-
41
15
12
12
150
30
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
26
LE to Qn; see Figure 9
VCC = 2.0 V
-
-
-
-
50
18
15
14
175
35
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
30
[2]
[3]
[4]
ten
tdis
tt
enable time
OE to Qn; see Figure 10
VCC = 2.0 V
-
-
-
44
16
13
150
30
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
26
disable time
OE to Qn; see Figure 10
VCC = 2.0 V
-
-
-
47
17
14
150
30
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
26
transition time
pulse width
Qn; see Figure 8 and Figure 9
VCC = 2.0 V
-
-
-
14
5
60
12
10
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
4
tW
tsu
th
LE HIGH; see Figure 9
VCC = 2.0 V
80
16
14
17
6
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
5
set-up time
Dn to LE; see Figure 11
VCC = 2.0 V
50
10
9
14
5
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
4
hold time
Dn to LE; see Figure 11
VCC = 2.0 V
+5
+5
+5
-
8
3
2
45
-
-
-
-
ns
ns
ns
pF
VCC = 4.5 V
VCC = 6.0 V
[5]
CPD
power dissipation capacitance
per latch; VI = GND to VCC
74HC_HCT373_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 10 August 2012
10 of 24
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