ADP3212/NCP3218
voltage that are being switched. Basing the switching speed on
the rise and fall times of the gate driver impedance and
MOSFET input capacitance, the following expression provides
an approximate value for the switching loss per main MOSFET:
POWER MOSFETS
For typical 20 A per phase applications, the N-channel power
MOSFETs are selected for two high-side switches and two or
three low-side switches per phase. The main selection
parameters for the power MOSFETs are VGS(TH), QG, CISS, CRSS
and RDS(ON). Because the voltage of the gate driver is 5 V, logic-
level threshold MOSFETs must be used.
V
DC × IO
nMF
nMF
n
,
PS(MF) = 2× fSW
×
× RG ×
×CISS
(15)
where:
MF is the total number of main MOSFETs.
RG is the total gate resistance.
ISS is the input capacitance of the main MOSFET.
n
The maximum output current, IO, determines the RDS(ON)
requirement for the low-side (synchronous) MOSFETs. In the
ADP3212/NCP3218, currents are balanced between phases; the
current in each low-side MOSFET is the output current divided
by the total number of MOSFETs (nSF). With conduction losses
being dominant, the following expression shows the total power
that is dissipated in each synchronous MOSFET in terms of the
ripple current per phase (IR) and the average total output
current (IO):
C
The most effective way to reduce switching loss is to use lower
gate capacitance devices.
The conduction loss of the main MOSFET is given by the
following equation:
2
2
⎡
⎢
⎤
⎥
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
IO
nMF
n×IR
nMF
1
12
2
2
PC(MF) = D×
+
×
×RDS(MF)
(16)
⎡
⎢
⎤
⎥
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
IO
nSF
n×IR
nSF
1
12
⎢
⎣
⎥
⎦
PSF = (1− D)×
+
×
×RDS(SF)
(14)
⎢
⎣
⎥
⎦
where RDS(MF) is the on resistance of the MOSFET.
where:
Typically, a user wants the highest speed (low CISS) device
D is the duty cycle and is approximately the output voltage
divided by the input voltage.
IR is the inductor peak-to-peak ripple current and is
approximately
for a main MOSFET, but such a device usually has higher on
resistance. Therefore, the user must select a device that meets
the total power dissipation (about 0.8 W to 1.0 W for an 8-lead
SOIC) when combining the switching and conduction losses.
(1− D)×VOUT
IR
=
L× fSW
For example, an IRF7821 device can be selected as the main
MOSFET (four in total; that is, nMF = 4), with approximately
Knowing the maximum output current and the maximum
allowed power dissipation, the user can calculate the required
DS(ON) for the MOSFET. For 8-lead SOIC or 8-lead SOIC-
CISS = 1010 pF (maximum) and RDS(MF) = 18 mΩ (maximum at
TJ = 120°C), and an IR7832 device can be selected as the
synchronous MOSFET (four in total; that is, nSF = 4), with
RDS(SF) = 6.7 mΩ (maximum at TJ = 120°C). Solving for the
power dissipation per MOSFET at IO = 40 A and IR = 9.0 A
yields 630 mW for each synchronous MOSFET and 590 mW
for each main MOSFET. A third synchronous MOSFET is an
option to further increase the conversion efficiency and reduce
thermal stress.
R
compatible MOSFETs, the junction-to-ambient (PCB) thermal
impedance is 50°C/W. In the worst case, the PCB temperature is
70°C to 80°C during heavy load operation of the notebook, and
a safe limit for PSF is about 0.8 W to 1.0 W at 120°C junction tem-
perature. Therefore, for this example (40 A maximum), the RDS(SF)
per MOSFET is less than 8.5 mΩ for two pieces of low-side
MOSFETs. This RDS(SF) is also at a junction temperature of about
120°C; therefore, the RDS(SF) per MOSFET should be less than
6 mΩ at room temperature, or 8.5 mΩ at high temperature.
Finally, consider the power dissipation in the driver for each
phase. This is best described in terms of the QG for the
MOSFETs and is given by the following equation:
Another important factor for the synchronous MOSFET is the
input capacitance and feedback capacitance. The ratio of the
feedback to input must be small (less than 10% is recommended)
to prevent accidentally turning on the synchronous MOSFETs
when the switch node goes high.
f
⎡
⎤
SW
PDRV
=
×
(
n
MF ×QGMF +nSF ×QGSF
)
+ ICC ×VCC
(17)
⎢
⎥
2×n
⎣
⎦
where QGMF is the total gate charge for each main MOSFET, and
GSF is the total gate charge for each synchronous MOSFET.
Q
The high-side (main) MOSFET must be able to handle two
main power dissipation components: conduction losses and
switching losses. Switching loss is related to the time for the
main MOSFET to turn on and off and to the current and
The previous equation also shows the standby dissipation (ICC
times the VCC) of the driver.
Rev. SpA | Page 32 of 43
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