ADP3212/NCP3218
For example, if 30 pieces of 10 μF, 0805-size MLC capacitors
(CZ = 300 μF) are used, the fastest VID voltage change is when
the device exits deeper sleep, during which the VCORE change is
220 mV in 22 μs with a setting error of 10 mV. If k = 3.1, solving
for the bulk capacitance yields
COUT SELECTION
The required output decoupling for processors and platforms is
typically recommended by Intel. For systems containing both
bulk and ceramic capacitors, however, the following guidelines
can be a helpful supplement.
⎛
⎜
⎞
⎟
Select the number of ceramics and determine the total ceramic
capacitance (CZ). This is based on the number and type of
capacitors used. Keep in mind that the best location to place
ceramic capacitors is inside the socket; however, the physical
limit is twenty 0805-size pieces inside the socket. Additional
ceramic capacitors can be placed along the outer edge of the
socket. A combined ceramic capacitor value of 200 μF to 300 μF
is recommended and is usually composed of multiple 10 μF or
22 μF capacitors.
⎜
⎜
⎜
⎟
330 nH × 27.9 A
⎟
CX
CX
≥
≤
−300 ꢀF =1.0 mF
(
MIN )
⎛
⎜
⎝
⎞
⎟
⎟
⎠
⎟
10 mV
27.9 A
⎜
2 × 2.1 mꢁ+
×1.4375 V
⎜
⎜
⎝
⎟
⎟
⎠
330 nH × 220 mV
2 ×3.12 ×(2.1mꢁ)2 ×1.4375V
×
(
MAX
)
2
⎛
⎜
⎞
⎟
⎛
⎞
⎟
⎟
⎠
22 ꢀs ×1.4375 V × 2 × 3.1× 2.1 mꢁ
220 mV × 490 nH
⎜
⎜
⎝
1+
−1 −300 ꢀF
⎜
⎟
⎜
⎝
⎟
⎠
Ensure that the total amount of bulk capacitance (CX) is within
its limits. The upper limit is dependent on the VID on-the-fly
output voltage stepping (voltage step, VV, in time, tV, with error
of VERR); the lower limit is based on meeting the critical capacitance
for load release at a given maximum load step, ΔIO. The current
version of the IMVP-6.5 specification allows a maximum VCORE
overshoot (VOSMAX) of 10 mV more than the VID voltage for a
step-off load current.
= 21 mF
Using six 330 μF Panasonic SP capacitors with a typical ESR of
7 mΩ each yields CX = 1.98 mF and RX = 1.2 mΩ.
Ensure that the ESL of the bulk capacitors (LX) is low enough to
limit the high frequency ringing during a load change. This is
tested using
⎛
⎜
⎞
⎟
LX ≤ CZ × RO 2 × Q2
(13)
⎜
⎜
⎜
⎜
⎝
⎟
⎟
⎟
⎟
⎠
L × ΔIO
CX
≥
MIN )
−CZ
(11)
(
⎛
⎞
⎟
⎟
⎠
VOSMAX
LX ≤ 300 ꢀF × 2.1 mꢁ
)
2 ×2 = 2 nH
⎜
n × RO +
×VVID
⎜
ΔIO
⎝
where:
2
⎛
⎜
⎞
Q is limited to the square root of 2 to ensure a critically damped
system.
⎛
⎞
⎟
⎟
⎠
L
VV
VVID n×k ×RO
⎟
⎜
CX(MAX)
≤
×
×
1+ tv
×
−1 −CZ
⎜
⎜
⎝
⎟
n×k2 ×RO2 VVID
VV
L
⎜
⎟
⎠
⎝
LX is about 150 pH for the six SP capacitors, which is low
enough to avoid ringing during a load change. If the LX of the
chosen bulk capacitor bank is too large, the number of ceramic
capacitors may need to be increased to prevent excessive
ringing.
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
VERR
VV
k = −ln
where
(12)
To meet the conditions of these expressions and the transient
response, the ESR of the bulk capacitor bank (RX) should be less
than two times the droop resistance, RO. If the CX(MIN) is greater
than CX(MAX), the system does not meet the VID on-the-fly
and/or the deeper sleep exit specifications and may require less
inductance or more phases. In addition, the switching frequency
may have to be increased to maintain the output ripple.
For this multimode control technique, an all ceramic capacitor
design can be used if the conditions of Equations 11, 12, and 13
are satisfied.
Rev. SpA | Page 31 of 43
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