––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ ML53612 ■
Configuration Register Byte 12, AR = 000ch
DR_0
C
Definition
0
1
2
3
4
5
6
7
96
Direct Parallel Access Enable
Microprocessor Watchdog Enable
APLL Clock Watchdog Enable
Reserved
97
98
99
100
101
102
103
Message Channel Registered TXD Enable
Message Channel Output Disable
Reserved
Reserved
Direct Parallel Access Enable (C_ [96]) (Read/Write)
0
1
→
→
Direct Parallel Access disabled (Default)
Direct Parallel Access enabled
Microprocessor Watchdog Enable (C_ [97]) (Read/Write)
When enabled, the ML53612 enters into reset after the Analog PLL clocks for 256mS ( 50ꢀ).
Each time C_[97] is cleared (0) and then set (1), the microprocessor watchdog count is reset.
0
1
→
→
Microprocessor Watchdog disabled (Default)
Microprocessor Watchdog enabled
APLL Clock Watchdog Enable (C_ [98]) (Read/Write)
When enabled, C_[98] will read back as being set (1) until the Analog PLL clocks for 125 µS ( 50ꢀ), then will read back as being cleared (0). Each
time C_[98] is cleared (0) and then set (1), the clock watchdog count is reset.
0
1
→
→
APLL Clock Watchdog disabled (Default)
APLL Clock Watchdog enabled
Message Channel Registered TXD Enable (C_ [100]) (Read/Write)
0
1
→
→
MC_TXD passed though to CT_MC (Default)
MC_TXD registered to CT_MC on rising edge of MC_CLK
Message Channel Output Disable with Loop-back (C_ [101]) (Read/Write)
When CT_MC output is disabled, the local message channel circuitry can be tested without disturbing the CT Bus.
0
1
→
→
CT_MC Output enabled (Default)
CT_MC Output Tri-stated, MC_TXD looped back to MC_RXD
Oki Semiconductor
29
OKI [ OKI ELECTRONIC COMPONETS ]
