■ ML53612 ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
Configuration Register Byte 15, AR = 000fh
DR_0
C
Definition
0
1
2
3
4
5
6
7
120
121
122
123
124
125
126
127
CT Bus A Error Latch Clear
CT Bus B Error Latch Clear
SCbus Error Latch Clear
MVIP Error Latch Clear
Master PLL Error Latch Clear
Frame Boundary Latch Clear
Reserved
Reserved
CT Bus A Error Latch Clear (C_ [120]) (Read/Write)
0
1
→
→
CT Bus A Error Latch Enabled
CT Bus A Error Latch held clear (Default)
CT Bus B Error Latch Clear (C_ [121]) (Read/Write)
0
1
→
→
CT Bus B Error Latch Enabled
CT Bus B Error Latch held clear (Default)
SCbus Error Latch Clear (C_ [122]) (Read/Write)
0
1
→
→
SCbus Error Latch Enabled
SCbus Error Latch held clear (Default)
MVIP Error Latch Clear (C_ [123]) (Read/Write)
0
1
→
→
MVIP Error Latch Enabled
MVIP Error Latch held clear (Default)
Master PLL Error Latch Clear (C_ [124]) (Read/Write)
0
1
→
→
Master PLL Error Latch Enabled
Master PLL Error Latch held clear (Default)
Frame Boundary Latch Clear (C_ [125]) (Read/Write)
0
1
→
→
Frame Boundary Latch Enabled
Frame Boundary Latch held clear (Default)
32
Oki Semiconductor
OKI [ OKI ELECTRONIC COMPONETS ]
