––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ ML53612 ■
Configuration Register Byte 14, AR = 000eh [1]
DR_0
C
Definition
0
1
2
3
4
5
6
7
112
113
114
115
116
117
118
119
CT Bus A Error Interrupt Mask
CT Bus B Error Interrupt Mask
SCbus Error Interrupt Mask
MVIP Error Interrupt Mask
Master PLL Error Interrupt Mask
Frame Boundary Interrupt Mask
Reserved
Reserved
1. Masking an interrupt disables that interrupt from being OR’ed together with other interrupts to the INT pin. The state of the latches are accessible
while masked (polling mode).
CT Bus A Error Interrupt Mask (C_ [112]) (Read/Write)
0
1
→
→
CT Bus A Error Interrupt Unmasked
CT Bus A Error Interrupt Masked (Default)
CT Bus B Error Interrupt Mask (C_ [113]) (Read/Write)
0
1
→
→
CT Bus B Error Interrupt Unmasked
CT Bus B Error Interrupt Masked (Default)
SCbus Error Interrupt Mask (C_ [114]) (Read/Write)
0
1
→
→
SCbus Error Interrupt Unmasked
SCbus Error Interrupt Masked (Default)
MVIP Error Interrupt Mask (C_ [115]) (Read/Write)
0
1
→
→
MVIP Error Interrupt Unmasked
MVIP Error Interrupt Masked (Default)
Master PLL Error Interrupt Mask (C_ [116]) (Read/Write)
0
1
→
→
Master PLL Error Interrupt Unmasked
Master PLL Error Interrupt Masked (Default)
Frame Boundary Interrupt Mask (C_ [117]) (Read/Write)
0
1
→
→
Frame Boundary Interrupt Unmasked
Frame Boundary Interrupt Masked (Default)
Oki Semiconductor
31
OKI [ OKI ELECTRONIC COMPONETS ]
